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enhanced a/d type 8-bit otp mcu with opa HT46R064G/065g/0662g revision: 1.00 date: march 3, 2011
table of contents features ...............................................................................................1 cpu features ........................................................................................................1 peripheral features ................................................................................................1 general description ............................................................................2 selection table ....................................................................................2 block diagram .....................................................................................2 pin assignment ...................................................................................3 pin description ....................................................................................4 HT46R064G ...........................................................................................................4 ht46r065g ...........................................................................................................5 ht46r0662g .........................................................................................................7 absolute maximum ratings .............................................................10 d.c. characteristics ..........................................................................10 a.c. characteristics ..........................................................................12 adc characteristics..........................................................................13 power-on reset characteristics ......................................................14 comparator amplifier characteristics ............................................14 operational amplifier characteristics.............................................14 system architecture .........................................................................15 clocking and pipelining ........................................................................................15 program counter ..................................................................................................16 stack ....................................................................................................................17 arithmetic and logic unit alu ...........................................................................17 program memory...............................................................................18 structure ...............................................................................................................18 special vectors .....................................................................................................18 look-up table .......................................................................................................19 table program example .......................................................................................20 data memory......................................................................................21 structure ...............................................................................................................21 rev. 1.00 2 march 3, 2011 contents
special purpose data memory.........................................................22 special function registers ...................................................................................23 wake-up function register pawk, pcwk ........................................................28 pull-high registers papu, pbpu, pcpu, pdpu, pepu, pfpu ........................28 software com register scomc .......................................................................28 oscillator............................................................................................28 system oscillator overview ..................................................................................28 system clock configurations ................................................................................29 external crystal/resonator oscillator hxt ........................................................29 external rc oscillator erc ...............................................................................30 internal rc oscillator hirc ...............................................................................30 external 32768hz crystal oscillator lxt ...........................................................31 lxt oscillator low power function ......................................................................31 internal low speed oscillator lirc ...................................................................32 operating modes ...............................................................................32 mode types and selection ...................................................................................32 mode switching ....................................................................................................34 standby current considerations ...........................................................................34 wake-up ...............................................................................................................35 watchdog timer ................................................................................36 watchdog timer operation ...................................................................................36 reset and initialisation .....................................................................38 reset functions ...................................................................................................38 reset initial conditions .........................................................................................41 input/output ports.............................................................................44 pull-high resistors ................................................................................................44 i/o port wake-up ..................................................................................................44 i/o port control registers .....................................................................................46 pin-shared functions ............................................................................................46 pin remapping configuration ht46r0662g .....................................................49 i/o pin structures .................................................................................................49 programming considerations ...............................................................................49 timer/event counters .......................................................................50 configuring the timer/event counter input clock source .....................................50 timer registers tmr0, tmr1 ...........................................................................50 timer control registers tmr0c, tmr1c ..........................................................52 timer mode ..........................................................................................................53 event counter mode .............................................................................................54 pulse width capture mode ...................................................................................54 prescaler ..............................................................................................................55 pfd function .......................................................................................................55 contents rev. 1.00 iii march 3, 2011
i/o interfacing .......................................................................................................56 timer program example .......................................................................................57 time base ..........................................................................................57 pulse width modulator .....................................................................58 pwm operation ....................................................................................................58 6+2 pwm mode ...................................................................................................59 7+1 pwm mode ...................................................................................................60 pwm output control ............................................................................................61 pwm programming example ...............................................................................61 analog to digital converter..............................................................62 a/d overview .......................................................................................................62 a/d converter data registers adrl, adrh .....................................................63 a/d converter control registers adcr, acsr, ancsr ..................................63 a/d operation .......................................................................................................66 a/d input pins ......................................................................................................67 summary of a/d conversion steps ......................................................................68 programming considerations ...............................................................................70 a/d transfer function ...........................................................................................70 a/d programming example ..................................................................................71 operational amplifiers......................................................................72 comparator & operational amplifier registers .....................................................72 operational amplifier operation ............................................................................72 operational amplifier application example ...........................................................76 operational amplifier offset cancellation function ...............................................83 comparator ........................................................................................84 comparator functions ..........................................................................................84 interrupts............................................................................................86 interrupt register ..................................................................................................86 interrupt operation ...............................................................................................88 interrupt priority .....................................................................................................90 external interrupt ..................................................................................................91 timer/event counter interrupt ..............................................................................91 a/d converter interrupt ........................................................................................91 time base interrupt ..............................................................................................91 multi-function interrupt ..........................................................................................92 programming considerations ...............................................................................92 scom function for lcd ...................................................................92 lcd operation .....................................................................................................92 lcd bias control ..................................................................................................93 configuration options ......................................................................94 application circuits ..........................................................................94 rev. 1.00 iv march 3, 2011 contents
instruction set ...................................................................................95 introduction ..........................................................................................................95 instruction timing .................................................................................................95 moving and transferring data ..............................................................................95 arithmetic operations ...........................................................................................95 logical and rotate operations .............................................................................95 branches and control transfer .............................................................................96 bit operations .......................................................................................................96 table read operations .........................................................................................96 other operations ..................................................................................................96 instruction set summary ......................................................................................97 instruction definition ........................................................................99 package information .......................................................................109 16-pin dip (300mil) outline dimensions .............................................................109 16-pin nsop (150mil) outline dimensions .........................................................112 20-pin dip (300mil) outline dimensions .............................................................113 20-pin sop (300mil) outline dimensions ............................................................115 20-pin ssop (150mil) outline dimensions .........................................................116 24-pin skdip (300mil) outline dimensions .........................................................117 24-pin sop (300mil) outline dimensions ............................................................120 24-pin ssop (150mil) outline dimensions .........................................................121 28-pin skdip (300mil) outline dimensions ........................................................122 28-pin sop (300mil) outline dimensions ............................................................123 28-pin ssop (150mil) outline dimensions .........................................................124 44-pin qfp (10mm 10mm) outline dimensions ................................................125 reel dimensions ................................................................................................126 carrier tape dimensions ....................................................................................127 contents rev. 1.00 v march 3, 2011
features cpu features operating voltage: f sys = 4mhz: 2.2v~5.5v f sys = 8mhz: 3.3v~5.5v f sys = 12mhz: 4.5v~5.5v up to 0.33 s instruction cycle with 12mhz system clock at v dd =5v oscillator types: external high freuency crystal -- hxt external rc -- erc internal rc -- hirc external low frequency crystal -- lxt four operational modes: normal, slow, idle, sleep fully integrated internal 4mhz, 8mhz and 12mhz oscillator requires no external components watchdog timer function lirc oscillator function for watchdog timer all instructions executed in one or two instruction cycles table read instructions 63 powerful instructions up to 6-level subroutine nesting bit manipulation instruction low voltage reset function wide range of available package types peripheral features program memory: 1k x 14 ~ 4k x 15 data memory: 6 4x8~224x8 up to 42 bidirectional i/o lines up to 8 channel 12-bit adc up to 2 channel 8-bit pwm software controlled 4-scom lines lcd driver with 1 / 2 bias external interrupt input shared with an i/o line up to two 8-bit programmable timer/event counter with overflow interrupt and prescaler time-base function programmable frequency divider -- pfd two integrated operational amplifiers with interrupt function -- one with programmable gain control single comparator with interrupt and low power consumption rev. 1.00 6 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa
general description the enhanced a/d mcu devices are a series of 8-bit high performance, risc architecture microcontroller specifically designed for a wide range of applications. the usual holtek microcontroller features of low power consumption, i/o flexibility, timer functions, oscillator options, power down and wake-up functions, watchdog timer and low voltage reset, combine to provide devices with a huge range of functional options while still maintaining a high level of cost effectiveness. the fully integrated system oscillator hirc, which requires no external components and which has three frequency selections, opens up a huge range of new application possibilities for the device, some of which may include industrial control, consumer products, household appliances subsystem controllers, etc. selection table part no. program memory data memory i/o 8-bit timer hirc (mhz) rtc (lxt) lcd scom a/d pwm opa comp. pfd stack package HT46R064G 1k 14 64 8 18 1 4/8/12 12-bit 2 8-bit 12 1 4 16dip/nsop 20dip/sop/ssop ht46r065g 2k 15 96 8 22 1 4/8/12 4 12-bit 4 8-bit 12 1 4 16dip/nsop 20dip/sop/ssop 24skdip/sop/ssop ht46r0662g 4k 15 224 8 42 2 4/8/12 (*) 4 12-bit 8 8-bit 22 1 6 24/28skdip/sop/ssop 44qfp note: * the oscillator is connected to the osc3/osc4 pins with tinypowertm design. block diagram the following block diagram illustrates the main functional blocks. HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 7 march 3, 2011
! " # $ % & '
( ! ) ' * ) ) + $ )
$ & ) + ' ) +
' '
pin assignment note: bracketed pin names indicate non-default pinout remapping locations. rev. 1.00 8 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa # # ) ) ' $ , & - ' $ . & / ' $ 0 & ' , & 1 ' * ) 2 & $ 3 4 ' 5 & 1
4 2 & $ 3 / & # * ' 6 & 1 3
2 & $ 3 - ' - & 1
/ 2 & $ 3 6 ' ) 0 & $ 3 5 ' ) . & $ 3 , ' * / & 6 ' * 4 & 5 ' ( 6 & 1
/ 2 & 6 ' $ 5 & ' 4 & $ 4 ' # # ) ) ' $ , & - ' $ . & / ' $ 0 & ' , & $ 3 4 ' 5 & $ 3 /
/ . / , / 5 / 6 / - / / / 4 7 7 8 / - 6 5 , . 0
' $ 5 & ' 4 & $ 4 ' ' $ 6 & 3
& $ 4 3 ' $ - &
4 & $ 4 9 ' $ / & ' * ) & $ / 9 ' $ 4 & $ / 3 ' . & $ / ' ' 0 & ' ' 4 & 3 ' / & 9 ' ( 4 # # ) ) ' $ , & - ' $ . & / ' $ 0 & ' , & $ 3 4 ' 5 & $ 3 / ' ( 6 ' ( - ' ( / ' $ 6 & 3
& $ 4 3 ' $ - &
4 & $ 4 9 ' $ / & ' * ) & $ / 9 ' $ 4 & $ / 3 ' . & $ / ' ' 0 & ' ' 4 & 3 ' / & 9 - 4 / 8 / / 0 / . / , / 5 / 6 / - / / / - 6 5 , . 0 8 / 4
' $ 5 &
/ ' & 4 & $ 4 ' # # ) ) ' $ , & - ' $ . & / ' $ 0 & ' , & $ 3 4 ' 5 & $ 3 / / . / , / 5 / 6 / - / / / 4 7 7 8 / - 6 5 , . 0 ' $ 6 & 3
& $ 4 3 ' $ - &
4 & $ 4 9 ' $ / & ' * ) & $ / 9 ' $ 4 & $ / 3 ' . & $ / ' ' 0 & ' ' 4 & 3 ' / & 9

- 5 - 6 - - - / - 4 / 8 / / 0 / . / , / 5 / 6 / - 6 5 , . 0 8 / 4 / / / - - 4 / 8 / / 0 / . / , / 5 / 6 / - / / / - 6 5 , . 0 8 / 4 ' $ 5 &
/ & ' 4 & $ 4 ' ' $ 6 & 3
& $ 4 3 ' $ - &
4 & $ 4 9 ' $ / & ' * ) & $ / 9 ' $ 4 & $ / 3 ' . & $ / ' ' 0 & ' ' 4 & 3 ' / & 9 ' ( 4 & 4 # # ) ) ' $ , & - ' $ . & / ' $ 0 & ' , & $ 3 4 ' 5 & $ 3 / ' ( 6 & 6 ' ( - & - ' ( / & / ' $ 5 &
/ & ' 4 & $ 4 ' ' $ 6 & 3
& $ 4 3 ' $ - &
4 & $ 4 9 ' $ / & ' * ) & $ / 9 ' $ 4 & $ / 3 ' . & $ / ' ' 0 & ' ' 4 & 3 ' / & 9 ' ( 4 & 4 ' ( / & / ' ( - & - # # ) ) ' $ , & - ' $ . & / ' $ 0 & ' , & $ 3 4 ' 5 & $ 3 / ' 6 & $ 3 - ' - & $ 3 6 ' ( , ' ( 5 ' ( 6 & 6
' $ 5 &
/ & $ 4 ' ' $ 6 & 3
& $ 4 3 ' $ - &
4 & $ 4 9 ' $ / & ' * ) & $ / 9 ' $ 4 & $ / 3 ' . & $ / ' ' 0 & ' ' 4 & 3 ' / & 9 ' ) 4 & ' 4 ' ( 4 & 1 ' * ) 2 & 4 ' ( / & 1
4 2 & / # # ) ) ' $ , & - ' $ . & / ' $ 0 & ' , & 1 ' * ) 2 & $ 3 4 ' 5 & 1
4 2 & $ 3 / & # * ' 6 & 1 3
2 & $ 3 - ' * / & 6 ' * 4 & 5 ' ( 6 & 1
/ 2 & 6 ' ( - & 1 3
2 & - - 5 - 6 - - - / - 4 / 8 / / 0 / . / , / 5 / 6 / - 6 5 , . 0 8 / 4 / / / - ' $ 0 & ' $ . & / ' $ , & - # ) ) # ' $ 5 &
/ & $ 4 ' ' $ 6 & 3
& $ 4 3 ' $ - &
4 & $ 4 9 ' $ / & ' * ) & $ / 9 ' $ 4 & $ / 3 ' . & $ / ' ' , & 1 ' * ) 2 & $ 3 4 ' 5 & 1
4 2 & $ 3 / & # * ' 6 & 1 3
2 & $ 3 - ' - & 1
/ 2 & $ 3 6 ' ) 0 & $ 3 5 ' ) . & $ 3 , ' ) , & $ 3 . ' ) 5 & $ 3 0 ' ) 6 ' ) - ' * / & 6
/ - 6 5 , . 0 8 / 4 / / / - / 6 / 5 / , / . / 0 / / 8 - 4 - / - - - 6 - 5 - , - . - 0 - - 8 6 4 6 / 6 - 6 6 6 56 ,6 .6 06 6 85 45 /5 -5 65 5 ' * 4 & 5 ' ( 0 ' ( . ' ( , ' ( 5 ' ( 6 & 1
/ 2 & 6 ' ( - & 1 3
2 & - ' ( / & 1
4 2 & / ' ( 4 & 1 ' * ) 2 & 4 ' ) / & ' / ' ) 4 & ' 4 ' 0 & ' ' 4 & 3 ' / & $ 9 ' 4 & 1 ' * ) 2 ' / & 1
4 2 ' - & 1 3
2 ' 6 & 1
/ 2 ' 5 ' , ' . ' 0
- - 0 - . - , - 5 - 6 - - - / - 4 / 8 / / 0 / . / , / - 6 5 , . 0 8 / 4 / / / - / 6 / 5 ' $ 5 &
/ & $ 4 ' ' $ 6 & 3
& $ 4 3 ' $ - &
4 & $ 4 9 ' $ / & ' * ) & $ / 9 ' $ 4 & $ / 3 ' . & $ / ' ' 0 & ' ' 4 & 3 ' / & 9 ' ) 4 & ' 4 ' ) / & ' / ' ( 4 & 1 ' * ) 2 & 4 ' ( / & 1
4 2 & / ' ( - & 1 3
2 & -
pin description the function of each pin is listed in the following tables, however the details behind how each pin is configured is contained in the other individual peripheral function sections. HT46R064G pin name function opt i/t o/t description pa0/a1n pa0 papu pawk st cmos general purpose i/o. register enabled pull-up and wake-up. a1n copa3c opai opa1 inverting input pin pa1/pfd/a1x pa1 papu pawk st cmos general purpose i/o. register enabled pull-up and wake-up. pfd ctrl0 cmos pfd output a1x copa3c opao opa1 output pin pa2/tc0/a0x pa2 papu pawk st cmos general purpose i/o. register enabled pull-up and wake-up. tc0 tmr0c st external timer 0 clock input a0x copa3c opao opa0 output pin pa3/int/a0n pa3 papu pawk st cmos general purpose i/o. register enabled pull-up and wake-up. int intc0 ctrl1 st external interrupt input a0x copa3c opai opa0 inverting input pin pa4/pwm0/a0p pa4 papu pawk st cmos general purpose i/o. register enabled pull-up and wake-up. pwm0 ctrl0 cmos pwm output a0p copa3c opai opa0 non-inverting input pin pa5/osc2 pa5 papu pawk st cmos general purpose i/o. register enabled pull-up and wake-up. osc2 co osc oscillator pin pa6/osc1 pa6 papu pawk st cmos general purpose i/o. register enabled pull-up and wake-up. osc1 co osc oscillator pin pa7/res pa7 pawk st nmos general purpose i/o. register enabled wake-up. res co st reset input pb0~pb3 pbn pbpu st cmos general purpose i/o. register enabled pull-up. pc0/cn pc0 pcpu st cmos general purpose i/o. register enabled pull-up. cn copa3c cmpi comparator inverting input pin pc1/cx pc1 pcpu st cmos general purpose i/o. register enabled pull-up. cx copa2c cmpo comparator output pin pc4/an1 pc4 pcpu st cmos general purpose i/o. register enabled pull-up. an1 adcr pcr an a/d channel 1 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 9 march 3, 2011
pin name function opt i/t o/t description pc5/an0 pc5 pcpu st cmos general purpose i/o. register enabled pull-up. an0 adcr pcr an a/d channel 0 pc6/a1p pc6 pcpu st cmos general purpose i/o. register enabled pull-up. a1p copa3c opai opa1 non-inverting input pin pc7/cp pc7 pcpu st cmos general purpose i/o. register enabled pull-up. cp copa3c cmpi comparator non-inverting input pin vdd vdd pwr power supply vss vss pwr ground note: opt: optional by configuration option (co) or register option i/t: input type o/t: output type pwr: power co: configuration option st: schmitt trigger input an: analog input; cmos: cmos output nmos: nmos output osc: oscillator pin opai: operational amplifier input opao: operational amplifier output cmpi: comparator input cmpo: comparator output ht46r065g pin name function opt i/t o/t description pa0/a1n pa0 papu pawk st cmos general purpose i/o. register enabled pull-up and wake-up. a1n copa3c opai opa1 inverting input pin pa1/pfd/a1x pa1 papu pawk st cmos general purpose i/o. register enabled pull-up and wake-up. pfd ctrl0 cmos pfd output a1x copa3c opao opa1 output pin pa2/tc0/a0x pa2 papu pawk st cmos general purpose i/o. register enabled pull-up and wake-up. tc0 tmr0c st external timer 0 clock input a0x copa3c opao opa0 output pin pa3/int/a0n pa3 papu pawk st cmos general purpose i/o. register enabled pull-up and wake-up. int intc0 ctrl1 st external interrupt input a0x copa3c opai opa0 inverting input pin rev. 1.00 10 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa
pin name function opt i/t o/t description pa4/tc1/pwm0/ a0p pa4 papu pawk st cmos general purpose i/o. register enabled pull-up and wake-up. tc1 tmr1c st external timer 1 clock input pwm0 ctrl0 cmos pwm output a0p copa3c opai opa0 non-inverting input pin pa5/osc2 pa5 papu pawk st cmos general purpose i/o. register enabled pull-up and wake-up. osc2 co osc oscillator pin pa6/osc1 pa6 papu pawk st cmos general purpose i/o. register enabled pull-up and wake-up. osc1 co osc oscillator pin pa7/res pa7 pawk st nmos general purpose i/o. register enabled wake-up. res co st reset input pb0/scom0~ pb3/scom3 pbn pbpu st cmos general purpose i/o. register enabled pull-up. scomn scomc scom software controlled 1/2 bias lcd com pb4~pb5 pbn pbpu st cmos general purpose i/o. register enabled pull-up. pc0/cn pc0 pcpu st cmos general purpose i/o. register enabled pull-up. cn copa3c cmpi comparator inverting input pin pc1/cx pc1 pcpu st cmos general purpose i/o. register enabled pull-up. cx copa2c cmpo comparator output pin pc2/an3 pc2 pcpu st cmos general purpose i/o. register enabled pull-up. an3 adcr pcr an a/d channel 3 pc3/an2 pc3 pcpu st cmos general purpose i/o. register enabled pull-up. an2 adcr pcr an a/d channel 2 pc4/an1 pc4 pcpu st cmos general purpose i/o. register enabled pull-up. an1 adcr pcr an a/d channel 1 pc5/an0 pc5 pcpu st cmos general purpose i/o. register enabled pull-up. an0 adcr pcr an a/d channel 0 pc6/a1p pc6 pcpu st cmos general purpose i/o. register enabled pull-up. a1p copa3c opai opa1 non-inverting input pin pc7/cp pc7 pcpu st cmos general purpose i/o. register enabled pull-up. cp copa3c cmpi comparator non-inverting input pin vdd vdd pwr power supply vss vss pwr ground note: opt: optional by configuration option (co) or register option i/t: input type; o/t: output type; pwr: power; co: configuration option st: schmitt trigger input; an: analog input cmos: cmos output; nmos: nmos output osc: oscillator pin; scom: software controlled lcd com cmpi: comparator input; cmpo: comparator output opai: operational amplifier input; opao: operational amplifier output HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 11 march 3, 2011
ht46r0662g pin name function opt i/t o/t description pa0/a1n pa0 papu pawk st cmos general purpose i/o. register enabled pull-up and wake-up. a1n copa3c opai opa1 inverting input pin pa1/pfd/a1x pa1 papu pawk st cmos general purpose i/o. register enabled pull-up and wake-up. pfd ctrl0 cmos pfd output a1x copa3c opao opa1 output pin pa2/tc0/a0x pa2 papu pawk st cmos general purpose i/o. register enabled pull-up and wake-up. tc0 tmr0c st external timer 0 clock input a0x copa3c opao opa0 output pin pa3/int/a0n pa3 papu pawk st cmos general purpose i/o. register enabled pull-up and wake-up. int intc0 ctrl1 st external interrupt input a0x copa3c opai opa0 inverting input pin pa4/tc1/a0p pa4 papu pawk st cmos general purpose i/o. register enabled pull-up and wake-up. tc1 tmr1c st external timer 1 clock input a0p copa3c opai opa0 non-inverting input pin pa5/osc2 pa5 papu pawk st cmos general purpose i/o. register enabled pull-up and wake-up. osc2 co osc oscillator pin pa6/osc1 pa6 papu pawk st cmos general purpose i/o. register enabled pull-up and wake-up. osc1 co osc oscillator pin pa7/res pa7 pawk st nmos general purpose i/o. register enabled wake-up. res co st reset input pb0/[pfd]/scom0 pb0 pbpu st cmos general purpose i/o. register enabled pull-up. pfd ctrl0 cmos pfd output scom0 scomc scom software controlled 1/2 bias lcd com pb1/[tc0]/scom1 pb1 pbpu st cmos general purpose i/o. register enabled pull-up. tc0 tmr0c st external timer 0 clock input scom1 scomc scom software controlled 1/2 bias lcd com pb2/[int]/scom2 pb2 pbpu st cmos general purpose i/o. register enabled pull-up. int intc0 ctrl1 st external interrupt input scom2 scomc scom software controlled 1/2 bias lcd com pb3/[tc1]/scom3 pb3 pbpu st cmos general purpose i/o. register enabled pull-up. tc1 tmr1c st external timer 1 clock input scom3 scomc scom software controlled 1/2 bias lcd com rev. 1.00 12 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa
pin name function opt i/t o/t description pb4~pb7 pbn pbpu st cmos general purpose i/o. register enabled pull-up. pc0/cn pc0 pcpu pcwk st cmos general purpose i/o. register enabled pull-up and wake-up. cn copa3c cmpi comparator inverting input pin pc1/cx pc1 pcpu pcwk st cmos general purpose i/o. register enabled pull-up and wake-up. cx copa2c cmpo comparator output pin pc2/[tc1]/an3 pc2 pcpu pcwk st cmos general purpose i/o. register enabled pull-up and wake-up. tc1 tmr1c st external timer 1 clock input an3 adcr ancsr an a/d channel 3 pc3/[int]/an2 pc3 pcpu pcwk st cmos general purpose i/o. register enabled pull-up and wake-up. int intc0 ctrl1 st external interrupt input an2 adcr ancsr an a/d channel 2 pc4/[tc0]/an1/ vref pc4 pcpu pcwk st cmos general purpose i/o. register enabled pull-up and wake-up. tc0 tmr0c st external timer 0 clock input an1 adcr ancsr an a/d channel 1 vref acsr an a/d converter reference input voltage pc5/[pfd]/an0 pc5 pcpu pcwk st cmos general purpose i/o. register enabled pull-up and wake-up. pfd ctrl0 cmos pfd output an0 adcr ancsr an a/d channel 0 pc6/a1p pc6 pcpu pcwk st cmos general purpose i/o. register enabled pull-up and wake-up. a1p copa3c opai opa1 non-inverting input pin pc7/cp pc7 pcpu pcwk st cmos general purpose i/o. register enabled pull-up and wake-up. cp copa3c cmpi comparator non-inverting input pin pd0/pwm0 pd0 pdpu st cmos general purpose i/o. register enabled pull-up. pwm0 ctrl0 cmos pwm 0 output pd1/pwm1 pd1 pdpu st cmos general purpose i/o. register enabled pull-up. pwm1 ctrl0 cmos pwm 1 output pd2~pd3 pdn pdpu st cmos general purpose i/o. register enabled pull-up. pd4/an7 pd4 pdpu st cmos general purpose i/o. register enabled pull-up. an7 adcr ancsr an a/d channel 7 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 13 march 3, 2011
pin name function opt i/t o/t description pd5/an6 pd5 pdpu st cmos general purpose i/o. register enabled pull-up. an6 adcr ancsr an a/d channel 6 pd6/an5 pd6 pdpu st cmos general purpose i/o. register enabled pull-up. an5 adcr ancsr an a/d channel 5 pd7/an4 pd7 pdpu st cmos general purpose i/o. register enabled pull-up. an4 adcr ancsr an a/d channel 4 pe0/[pfd] pe0 pepu st cmos general purpose i/o. register enabled pull-up. pfd ctrl0 cmos pfd output pe1/[tc0] pe1 pepu st cmos general purpose i/o. register enabled pull-up. tc0 tmr0c cmos external timer 0 clock input pe2/[int] pe2 pepu st cmos general purpose i/o. register enabled pull-up. int intc0 ctrl1 cmos external interrupt input pe3/[tc1] pe3 pepu st cmos general purpose i/o. register enabled pull-up. tc1 tmr1c cmos external timer 1 clock input pe4~pe7 pen pepu st cmos general purpose i/o. register enabled pull-up. pf0/osc4 pf0 pfpu st cmos general purpose i/o. register enabled pull-up. osc4 co osc lxt oscillator pin pf1/osc3 pf1 pfpu st cmos general purpose i/o. register enabled pull-up. osc3 co lxt lxt oscillator pin vdd vdd pwr power supply vss vss pwr ground note: opt: optional by configuration option (co) or register option i/t: input type o/t: output type pwr: power co: configuration option st: schmitt trigger input an: analog input cmos: cmos output nmos: nmos output hxt: high frequency crystal oscillator pin lxt: low frequency crystal oscillator pin scom: software controlled lcd com cmpi: comparator input cmpo: comparator output opai: operational amplifier input opao: operational amplifier output rev. 1.00 14 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa
absolute maximum ratings supply voltage ...............................................................................................v ss 0.3v to v ss +6.0v input voltage .................................................................................................v ss 0.3v to v dd +0.3v storage temperature ................................................................................................. 50 cto125 c operating temperature................................................................................................ 40 cto85 c i ol total.......................................................................................................................... .........100ma i oh total ................................................................................................................................ 100ma total power dissipation .........................................................................................................500mw note: these are stress ratings only. stresses exceeding the range specified under absolute maximum rat - ings may cause substantial damage to the device. functional operation of this device at other condi - tions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage f sys =4mhz 2.2 5.5 v f sys =8mhz 3.3 5.5 v f sys =12mhz 4.5 5.5 v i dd1 operating current (hxt, hirc, erc) 3v no load, f sys =4mhz 0.8 1.2 ma 5v 1.5 2.25 ma i dd2 operating current (hxt, hirc, erc) 3v no load, f sys =8mhz 1.4 2.1 ma 5v 2.8 4.2 ma i dd3 operating current (hxt, hirc, erc) 5v no load, f sys =12mhz 46ma i dd4 operating current (hirc + lxt, slow mode) 3v no load, f sys =32768hz (lxt on osc1/osc2, lvr disabled, lxtlp=1) 510 a 5v 12 24 a 3v no load, f sys =32768hz (lxt on xt1/xt2, lvr disabled, lxtlp=1) 510 a 5v 10 20 a i stb1 standby current (lirc on, lxt off) 3v no load, system halt 5 a 5v 10 a i stb2 standby current (lirc off, lxt off) 3v no load, system halt 1 a 5v 2 a i stb3 standby current (lirc off, lxt on, lxtlp=1) 3v no load, system halt (lxt on osc1/osc2) 5 a 5v 10 a 3v no load, system halt (lxt on xt1/xt2) 3 a 5v 5 a v il1 input low voltage for i/o, tcn and int 0 0.3v dd v HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 15 march 3, 2011
symbol parameter test conditions min. typ. max. unit v dd conditions v ih1 input high voltage for i/o, tcn and int 0.7v dd v dd v v il2 input low voltage (res ) 0 0.4v dd v v ih2 input high voltage (res ) 0.9v dd v dd v v lvr1 low voltage reset 1 vlvr = 4.2v 3.98 4.2 4.42 v v lvr2 low voltage reset 2 vlvr = 3.15v 2.98 3.15 3.32 v v lvr3 low voltage reset 3 vlvr = 2.1v 1.98 2.1 2.22 v i ol1 i/o port sink current (pa, pb, pc) 3v v ol =0.1v dd 48 ma 5v 10 20 ma i oh i/o port source current 3v v oh =0.9v dd 2 4 ma 5v 5 10 ma i ol2 pa7 sink current 5v v ol =0.1v dd 23 ma r ph pull-high resistance 3v 20 60 100 k
5v 10 30 50 k
i scom scom operating current 5v scomc, isel[1:0]=00 17.5 25.0 32.5 a scomc, isel[1:0]=01 35 50 65 a scomc, isel[1:0]=10 70 100 130 a scomc, isel[1:0]=11 140 200 260 a v scom v dd /2 voltage for lcd com 5v no load 0.475 0.500 0.525 v dd v opbias opa/comparator bias voltage deviation (bias=0.7/0.5/0.1v dd selected by a1ps[2:0], a0ps[2:0], cps[2:0] bits) 3v no load 0.665 0.700 0.735 v dd 0.475 0.500 0.525 v dd 0.995 0.100 0.105 v dd gop opa1 gain deviation (software gain controlled by a1g[2:0] 3v no load 5 +5 % note: the standby current (i stb1 ~i stb3 ) and i dd4 are measured with all i/o pins in input mode and tied to v dd . rev. 1.00 16 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa ta=25 c
a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys system clock 2.2v~5.5v 32 4000 khz 3.0v~5.5v 32 8000 khz 4.5v~5.5v 32 12000 khz f hirc system clock (hirc) 3v/5v ta=25 c 2% 4 +2% mhz 3v/5v ta=25 c 2% 8 +2% mhz 5v ta=25 c 2% 12 +2% mhz 3v/5v ta=0~70 c 5% 4 +5% mhz 3v/5v ta=0~70 c 5% 8 +5% mhz 5v ta=0~70 c 5% 12 +5% mhz 2.2v~ 3.6v ta=0~70 c 8% 4 +8% mhz 3.0v~ 5.5v ta=0~70 c 8% 4 +8% mhz 3.0v~ 5.5v ta=0~70 c 8% 8 +8% mhz 4.5v~ 5.5v ta=0~70 c 8% 12 +8% mhz 2.2v~ 3.6v ta= 40 c~85 c 12% 4 +12% mhz 3.0v~ 5.5v ta= 40 c~85 c 12% 4 +12% mhz 3.0v~ 5.5v ta= 40 c~85 c 12% 8 +12% mhz 4.5v~ 5.5v ta= 40 c~85 c 12% 12 +12% mhz f erc system clock (erc) 5v ta=25 c, r=120k
* 2% 4 +2% mhz 5v ta=0~70 c, r=120k
* 5% 4 +5% mhz 5v ta= 40 c~85 c, r=120k
* 7% 4 +7% mhz 2.2v~ 5.5v ta= 40 c~85 c, r=120k
* 11% 4 +11% mhz f lxt system clock (lxt) 32768 hz f timer timer input frequency (tcn) 2.2v~5.5v 0 4000 khz 3.0v~5.5v 0 8000 khz 4.5v~5.5v 0 12000 khz f lirc lirc oscillator 3v 5 10 15 khz 5v 6.5 13 19.5 khz t res external reset low pulse width 1 s HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 17 march 3, 2011
symbol parameter test conditions min. typ. max. unit v dd conditions t sst system start-up time period for hxt/lxt 128 t sys for erc/irc 2 t sys t int interrupt pulse width 1 s t lvr low voltage width to reset 0.25 1 2.00 ms t rstd reset delay time 50 ms note: 1. t sys =1/f sys 2. *for f erc , as the resistor tolerance will influence the frequency a precision resistor is recommended. 3. to maintain the accuracy of the internal hirc oscillator frequency, a 0.1 f decoupling capacitor should be connected between vdd and vss and located as close to the device as possible. adc characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v adi a/d converter input voltage 0 v ref v v ref a/d converter reference voltage 2 v dd v dnl a/c differential non-linearity t ad =0.5s 2 +2 lsb inl adc integral non-linearity t ad =0.5s 4 +4 lsb i adc additional power consumption if a/d converter is used 3v 0.50 0.75 ma 5v 1.00 1.50 ma t ad a/d converter clock period 2.7v~ 5.5v 0.5 10.0 s t adc a/d converter conversion time (including sample and hold time) 2.7v~ 5.5v 16 t ad t adcs a/d converter sampling time 2.7v~ 5.5v 4 t ad t on2st a/d converter on-to-start time 2.7v~ 5.5v 2 s rev. 1.00 18 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa ta=25 c
power-on reset characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v por vdd start voltage to ensure power-on reset 100 mv rr vdd vdd rise rate to ensure power-on reset 0.035 v/ms t por minimum time for vdd to remain at v por to ensure power-on reset 1 ms comparator amplifier characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions i comp comparator operating current 3v cpcs[1:0]=00b 200 300 a cpcs[1:0]=01b 510 a cpcs[1:0]=10b 12 a v os comparator input offset voltage 3v 10 10 mv v cm comparator common mode voltage range 0 v dd -1.4v v t pd comparator response time (with 10mv overdrive) 3v cpcs[1:0]=00b 2 s 3v cpcs[1:0]=01b 60 s cpcs[1:0]=10b 400 s operational amplifier characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions power down current 3v 0.1 a v opos1 input offset voltage 3v without calibration, opof[3:0]=1000b 15 15 mv v opos2 input offset voltage 3v by calibration 4 4mv v cm common mode voltage range v ss v dd -1.4v v psrr power supply rejection ratio 3v 60 80 db cmrr common mode rejection ratio 3v v cm =0~v dd 1.4v 60 80 db sr slew rate +, slew rate - 3v no load 1.8 2.5 v/s gbw gain band width 3v r l =1m, c l =100p 500 khz HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 19 march 3, 2011
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system architecture a key factor in the high-performance features of the holtek range of microcontrollers is attributed to the internal system architecture. the range of devices take advantage of the usual features found within risc microcontrollers providing increased speed of operation and enhanced performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. an 8-bit wide alu is used in practically all operations of the instruction set. it carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplified by moving data through the accumulator and the alu. certain internal registers are implemented in the data memory and can be directly or indirectly addressed. the simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional i/o and a/d control system with maximum reliability and flexibility. clocking and pipelining the main system clock, derived from either a crystal/resonator or rc oscillator is subdivided into four internally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way, one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. rev. 1.00 20 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa * 7 : 7 ; ' < 7 : 7 ; ' / < * 7 : 7 ; ' = / < 7 : 7 ; ' < * 7 : 7 ; ' = - < 7 : 7 ; ' = / < ' ' = / ' = - 7 > ; 7 > < ' 7 > 7
/ ' 7 ' 7 > 7
- ' 7 > 7
6 ' 7 > 7
5 ' system clocking and pipelining
for instructions involving branches, such as jump or call instructions, two instruction cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. program counter during program execution, the program counter is used to keep track of the address of the next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as jmp or call that demand a jump to a non-consecutive program memory address. note that the program counter width varies with the program memory capacity depending upon which device is selected. however, it must be noted that only the lower 8 bits, known as the program counter low register, are directly addressable by user. when executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the program counter. for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. device program counter program counter high byte pcl register HT46R064G pc9, pc8 pcl7~pcl0 ht46r065g pc10~pc8 ht46r662g pc11~pc8 the lower byte of the program counter, known as the program counter low register or pcl, is available for program control and is a readable and writeable register. by transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 loca - tions. when such program jumps are executed it should also be noted that a dummy cycle will be in - serted. the lower byte of the program counter is fully accessible under program control. manipulating the pcl might cause program branching, so an extra cycle is needed to pre-fetch. further information on the pcl register can be found in the special function register section. HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 21 march 3, 2011 * 7 : 7 / 7 : 7 / * 7 : 7 - * 7 ' / - 6 5 , . ) ! $ ? @ # 7 $ a 1 / - b 2 $ ! ! 7 ) ! $ ? ' ! 7 1 / - b 2 @ @ 3 ' 7 : 7 - * 7 : 7 6 * 7 : 7 . 7 : 7 . * 7 : 7 0 instruction fetching
stack this is a special part of the memory which is used to save the contents of the program counter only. the stack is neither part of the data or program memory space, and is neither readable nor writeable. the activated level is indexed by the stack pointer, sp, and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. device stack levels HT46R064G 4 ht46r065g/ht46r0662g 6 if the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overflow allowing the programmer to use the structure more easily. however, when the stack is full, a call subroutine instruction can still be executed which will result in a stack overflow. precautions should be taken to avoid such cases which might cause unpredictable program branching. arithmetic and logic unit alu the arithmetic-logic unit or alu is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. connected to the main microcontroller data bus, the alu receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. as these alu calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to reflect these changes. the alu supports the following functions: arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa logic operations: and, or, xor, andm, orm, xorm, cpl, cpla rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc increment and decrement inca, inc, deca, dec branch decision, jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti rev. 1.00 22 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa ' 7 > 7 ! + 7 / > 7 ! + 7 - > 7 ! + 7 6 > 7 ! + 7 3 '
7 % 7 > > ' ( 7 % 7 >
program memory the program memory is the location where the user code or program is stored. the device is supplied with one-time programmable, otp, memory where users can program their application code into the device. by using the appropriate programming tools, otp devices offer users the flexibility to freely develop their applications which may be useful during debug or for products requiring frequent upgrades or program changes. structure the program memory has a capacity of 1k 14 to 4k 15. the program memory is addressed by the program counter and also contains data, table information and interrupt entries. table data, which can be setup in any location within the program memory, is addressed by separate table pointer registers. device capacity HT46R064G 1k14 ht46r065g 2k15 ht46r0662g 4k15 special vectors within the program memory, certain locations are reserved for special usage such as reset and interrupts. reset vector this vector is reserved for use by the device reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution. external interrupt vector this vector is used by the external interrupt. if the external interrupt pin on the device receives an edge transition, the program will jump to this location and begin execution if the external interrupt is enabled and the stack is not full. the external interrupt active edge transition type, whether high to low, low to high or both is specified in the ctrl1 register. HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 23 march 3, 2011

! ! ! " # $ % & " # $ % & " # $ % & program memory structure
timer/event 0/1 counter interrupt vector this internal vector is used by the timer/event counters. if a timer/event counter overflow occurs, the program will jump to its respective location and begin execution if the associated timer/event counter interrupt is enabled and the stack is not full. a/d interrupt vector this vector is used by the a/d converter. if a completion of a/d conversion occurs, the program will jump to this location and begin execution if the a/d converter interrupt is enabled and the stack is not full. time base interrupt vector this vector is used by the opa0, opa1 and comparator. when either an opa or comparator, dependent upon which one is selected, requires interrupt servicing, the program will jump to this location and begin execution if the output interrupt is enabled and the stack is not full. look-up table any location within the program memory can be defined as a look-up table where programmers can store fixed data. to use the look-up table, the table pointer must first be setup by placing the lower order address of the look up data to be retrieved in the table pointer register, tblp. this register defines the lower 8-bit address of the look-up table. after setting up the table pointer, the table data can be retrieved from the current program memory page or last program memory page using the tabrdc[m] or tabrdl [m] instructions, respectively. when these instructions are executed, the lower order table byte from the program memory will be transferred to the user defined data memory register [m] as specified in the instruction. the higher order table data byte from the program memory will be transferred to the tblh special register. any unused bits in this transferred higher order byte will be read as 0 . the following diagram illustrates the addressing/data flow of the look-up table: instruction table location bits b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 tabrdc [m] pc11 pc10 pc9 pc8 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] 1 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0 table location note: pc11~pc8: current program counter bits @7~@0: table pointer tblp bits for the HT46R064G, the table address location is 10 bits, i.e. from b9~b0 for the ht46r065g, the table address location is 11 bits, i.e. from b10~b0 for the ht46r0662g, the table address location is 12 bits, i.e. from b11~b0 rev. 1.00 24 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa 7
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table program example the accompanying example shows how the table pointer and table data is defined and retrieved from the device. this example uses raw table data located in the last page which is stored there using the org statement. the value at this org statement is 300h which refers to the start address of the last page within the 1k program memory of the device. the table pointer is setup here to have an initial value of 06h . this will ensure that the first data read from the data table will be at the program memory address 306h or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the first address of the present page if the tabrdc [m] instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the tabrdl [m] instruction is executed. because the tblh register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and interrupt service routine use the table read instructions. if using the table read instructions, the interrupt service routines may change the value of tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. table read program example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise table pointer - note that this address is referenced mov tblp,a ; to the last page or present page : : tabrdl tempreg1 ; transfers value in table referenced by table pointer ; to tempregl ; data at prog. memory address 306h transferred to ; tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrdl tempreg2 ; transfers value in table referenced by table pointer ; to tempreg2 ; data at prog.memory address 305h transferred to ; tempreg2 and tblh ; in this example the data 1ah is transferred to ; tempreg1 and data 0fh to register tempreg2 ; the value 00h will be transferred to the high byte ; register tblh : : org 300h ; sets initial address of last page dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : : HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 25 march 3, 2011
data memory the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary information is stored. structure divided into two sections, the first of these is an area of ram where special function registers are located. these registers have fixed locations and are necessary for correct operation of the device. many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. the second area of data memory is reserved for general purpose use. all locations within this area are read and write accessible under program control. device capacity banks HT46R064G 648 ht46r065g 968 ht46r0662g 2248 0, 1 the two sections of data memory, the special purpose and general purpose data memory are located at consecutive locations. all are implemented in ram and are 8 bits wide but the length of each mem - ory section is dictated by the type of microcontroller chosen. the start address of the data memory for all devices is the address 00h . all microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. it is this area of ram memory that is known as general purpose data memory. this area of data memory is fully accessible by the user program for both read and write operations. by using the set [m].i and clr [m].i instructions individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the data memory. rev. 1.00 26 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa ' $ 4 4 4 b ' 4 4 / b $ 4 ' 4 d ' ( > 7 4 ( > 7 / $ 4 ' 4 $ 4 ' 4 8 * b 0 * b 5 4 b 6 * b . 5 7 8 . 7 * * b , * b
7 - - 5 7 $ / 4 4 b ' / 4 / b $ / ' / $ / ' / $ / ' / data memory structure note: most of the data memory bits can be directly manipulated using the set [m].i and clr [m].i with the exception of a few dedicated bits. the data memory can also be accessed through the memory pointer registers.
special purpose data memory this area of data memory is where registers, necessary for the correct operation of the microcontroller, are stored. most of the registers are both readable and writeable but some are protected and are readable only, the details of which are located under the relevant special function register section. note that for locations that are unused, any read instruction to these addresses will return the value 00h . HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 27 march 3, 2011 00h 01h 02h 03h HT46R064G iar0 mp0 iar1 mp1 04h acc 05h pcl 06h tblp 07h tblh 08h wdts 09h status 0ah intc0 0bh tmr0 0ch tmr0c 0dh 0eh 0fh pa 10h pac 11h papu 12h pawk 13h pb 14h pbc 15h pbpu 16h pc 17h pcc 18h pcpu 19h ctrl0 1ah ctrl1 1bh 1ch 1dh intc1 1eh pwm0 1fh adrl 20h adrh 21h adcr 22h acsr 23h 24h pcr 25h 26h 27h 28h cmp0c 29h cmp1c 2ah copa0c 2bh copa1c 2ch copa2c 2dh copa3c 2eh opa0oc 2fh opa1oc 30h 3fh ht46r065g iar0 mp0 iar1 mp1 acc pcl tblp tblh wdts status intc0 tmr0 tmr0c pa pac papu pawk pb pbc pbpu pc pcc pcpu ctrl0 ctrl1 intc1 pwm0 adrl adrh adcr acsr pcr cmp0c cmp1c copa0c copa1c copa2c copa3c opa0oc opa1oc tmr1 tmr1c lcdc mfic ht46r0662g iar0 mp0 iar1 mp1 acc pcl tblp tblh wdts status intc0 tmr0 tmr0c pa pac papu pawk pb pbc pbpu pc pcc pcpu ctrl0 ctrl1 intc1 pwm0 adrl adrh adcr acsr mfic tmr1 tmr1c lcdc pwm1 bp pd pdc pdpu cmp0c cmp1c copa0c copa1c copa2c copa3c opa0oc opa1oc pe pec pepu pf pfc pfpu ctrl2 31h 32h 33h 34h 35h 36h 37h 38h 39h 3ah ancsr0 pcwk 3eh : unused, read as 00h special purpose data memory
special function registers to ensure successful operation of the microcontroller, certain internal registers are implemented in the data memory area. these registers ensure correct operation of internal functions such as timers, interrupts, etc., as well as external functions such as i/o data control. the location of these registers within the data memory begins at the address 00h and are mapped into both bank 0 and bank 1. any unused data memory locations between these special function registers and the point where the general purpose memory begins is reserved and attempting to read data from these locations will return a value of 00h . indirect addressing registers iar0, iar1 the indirect addressing registers, iar0 and iar1, although having their locations in normal ram register space, do not actually physically exist as normal registers. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory addressing, where the actual memory address is specified. actions on the iar0 and iar1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding memory pointer, mp0 or mp1. acting as a pair, iar0 with mp0 and iar1 with mp1 can together access data from the data memory. as the indirect addressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of 00h and writing to the registers indirectly will result in no operation. memory pointers mp0, mp1 two memory pointers, known as mp0 and mp1 are provided. these memory pointers are physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to indirectly address and track data. mp0 can only be used to indirectly address data in bank 0 while mp1 can be used to address data in bank 0 and bank1. when any operation to the relevant indirect addressing registers is carried out, the actual address that the microcontroller is directed to, is the address specified by the related memory pointer. note that for the HT46R064G device, bit 7 of the memory pointers is not required to address the full memory space. when bit 7 of the memory pointers for these devices is read, a value of 1 will be returned. note that indirect addressing using mp1 and iar1 must be used to access any data in bank 1. the following example shows how to clear a section of four data memory locations already defined as locations adres1 to adres4. indirect addressing program example data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; accumulator loaded with first ram address mov mp0,a ; setup memory pointer with first ram address loop: clr iar0 ; clear the data at address defined by mp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: the important point to note here is that in the example shown above, no reference is made to specific data memory addresses. rev. 1.00 28 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa
accumulator acc the accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. without the accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the data memory resulting in higher programming and timing overheads. data transfer operations usually involve the temporary storage function of the accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register pcl to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory. by manipulating this register, direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specified program memory location, however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted. bank pointer bp in the ht46r0662g device, the data memory is divided into two banks, known as bank 0 and bank 1. a bank pointer, which is bit 0 of the bank pointer register is used to select the required data memory bank. only data in bank 0 can be directly addressed as data in bank 1 must be indirectly addressed using memory pointer mp1 and indirect addressing register iar1. using memory pointer mp0 and indirect addressing register iar0 will always access data from bank 0, irrespective of the value of the bank pointer. memory pointer mp1 and indirect addressing register iar1 can indirectly address data in either bank 0 or bank 1 depending upon the value of the bank pointer. the data memory is initialised to bank 0 after a reset, except for the wdt time-out reset in the idle/sleep mode, in which case, the data memory bank remains unaffected. it should be noted that special function data memory is not affected by the bank selection, which means that the special function registers can be accessed from within either bank 0 or bank 1. directly addressing the data memory will always result in bank 0 being accessed irrespective of the value of the bank pointer. bp register ht46r0662g b i t76543210 name dmbp0 r/w r/w por 0 bit 7~1 : unimplemented, read as 0 bit 0 dmbp0 : data memory bank point 0: bank 0 1: bank 1 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 29 march 3, 2011
status register status this 8-bit register contains the zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pdf), and watchdog time-out flag (to). these arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller. with the exception of the to and pdf flags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf flag. in addition, operations related to the status register may give different results due to the different instruction operations. the to flag can be affected only by a system power-up, a wdt time-out or by executing the clr wdt or halt instruction. the pdf flag is affected only by executing the halt or clr wdt instruction or during a system power-up. the z, ov, ac and c flags generally reflect the status of the latest operations. in addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status registers are important and if the interrupt routine can change the status register, precautions must be taken to correctly save it. note that bits 0~3 of the status register are both readable and writeable bits. status register b i t76543210 name to pdf ov z ac c r/w r r r/w r/w r/w r/w por 00xxxx x unknown bit 7, 6 unimplemented, read as 0 bit 5 to : watchdog time-out flag 0: after power up or executing the clr wdt or halt instruction 1: a watchdog time-out occurred. bit 4 pdf : power down flag 0: after power up or executing the clr wdt instruction 1: by executing the halt instruction bit 3 ov : overflow flag 0: no overflow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. bit 2 z : zero flag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero bit 1 ac : auxiliary flag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction bit 0 c: carry flag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation c is also affected by a rotate through carry instruction. rev. 1.00 30 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa
input/output ports and control registers within the area of special function registers, the port pa, pb, etc data i/o registers and their associated control register pac, pbc, etc play a prominent role. these registers are mapped to specific addresses within the data memory as shown in the data memory table. the data i/o registers, are used to transfer the appropriate output or input data on the port. the control registers specifies which pins of the port are set as inputs and which are set as outputs. to setup a pin as an input, the corresponding bit of the control register must be set high, for an output it must be set low. during program initialisation, it is important to first setup the control registers to specify which pins are outputs and which are inputs before reading data from or writing data to the i/o ports. one flexible feature of these registers is the ability to directly program single bits using the set [m].i and clr [m].i instructions. the ability to change i/o pins from output to input and vice versa by manipulating specific bits of the i/o control registers during normal program operation is a useful feature of these devices. system control registers ctrl0, ctrl1, ctrl2 these registers are used to provide control over several internal functions. these functions include the external interrupt edge trigger type, the pwm function control, time base period selection and lxt oscillator low power control,etc. ctrl0 register HT46R064G b i t76543210 name pwmsel pwmc0 pfdc lxtlp clkmod r/w r/w r/w r/w r/w r/w por 0 0000 ctrl0 register ht46r065g b i t76543210 name pfdcs pwmsel pwmc0 pfdc lxtlp clkmod r/w r/w r/w r/w r/w r/w r/w por 00 0000 ctrl0 register ht46r0662g b i t76543210 name pfdcs pwmsel pwmc1 pwmc0 pfdc lxtlp clkmod r/w r/w r/w r/w r/w r/w r/w r/w por 0000000 bit 7 unimplemented, read as 0 bit 6 pfdcs : pfd clock source selection 0: timer0 1: timer1 for HT46R064G device, this bit is read as 0 and the pfd clock source always comes from the timer. bit 5 pwmsel : pwm type selection 0: 6+2 type 1: 7+1 type bit 4 pwmc1 : i/o or pwm1 selection 0: i/o 1: pwm1 for the HT46R064G and ht46r065g devices, there is no pwm1 output. bit 3 pwmc0 : i/o or pwm0 selection 0: i/o or other pin-shared functions 1: pwm0 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 31 march 3, 2011
bit 2 pfdc : i/o or pfd selection 0: i/o 1: pfd bit 1 lxtlp : lxt oscillator low power control function 0: lxt oscillator quick start-up mode 1: lxt oscillator low power mode bit 0 clkmod : system clock mode selection 0: high speed - hirc oscillator used as system clock 1: low speed - lxt oscillator used as system clock, hirc oscillator stopped for HT46R064G/ht46r065g devices, this bit is available if the oscillator configuration options have selected the hirc+lxt. note: if the pwmn output is selected by the pwmcn bit, the pwm clock source f tp always comes from the system clock source f sys . the f tp clock is the clock source for timer0, timer 1, time base and pwm. ctrl1 register b i t76543210 name integ1 integ0 tbsel1 tbsel0 wdten3 wdten2 wdten1 wdten0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por10001010 bit 7, 6 integ1, integ0 : external interrupt edge type 00: disable 01: rising edge trigger 10: falling edge trigger 11: dual edge trigger bit 5, 4 tbsel1, tbsel0 : time base period selection 00: 2 10 /f tp 01: 2 11 /f tp 10: 2 12 1/f tp 11: 2 13 1/f tp bit 3~0 wdten3, wdten2, wdten1, wdten0 : wdt function enable 1010: wdt function disabled other values: wdt function enabled - recommended value is 0101 if the watchdog timer enable configuration option is selected, then the watchdog timer will always be enabled and the wdten3~wdten0 control bits will have no effect. note: the wdt is only disabled when both the wdt configuration option is disabled and when bits wdten3~wdten0 is set to 1010. the wdt is enabled when either the wdt configuration option is enabled or when bits wdten3~wdten0 1010. ctrl2 register ht46r0662g bit76543210 name pcfg1 pcfg0 lxten r/w r/w r/w r/w por 0 0 1 bit 7~6 pcfg1, pcfg0 : pin configuration 00: pfd/tc0/int/tc1 pin-shared with pa1/pa2/pa3/pa4 01: pfd/tc0/int/tc1 pin-shared with pc5/pc4/pc3/pc2 10: pfd/tc0/int/tc1 pin-shared with pb0/pb1/pb2/pb3 11: pfd/tc0/int/tc1 pin-shared with pe0/pe1/pe2/pe3 bit 5~1 unimplemented, read as 0 bit 0 lxten : lxt oscillator on/off control after execution of halt instruction 0: lxt oscillator off after halt instruction 1: lxt oscillator on after halt instruction rev. 1.00 32 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa
wake-up function register pawk, pcwk when the microcontroller enters the idle/sleep mode, various methods exist to wake the device up and continue with normal operation. one method is to allow a falling edge on the i/o pins to have a wake-up function. these register are used to selected which pins on i/o port a or port c are used to have this wake-up function. pull-high registers papu, pbpu, pcpu, pdpu, pepu, pfpu the i/o pins, if configured as inputs, can have internal pull-high resistors connected, which eliminates the need for external pull-high resistors. this register selects which i/o pins are connected to internal pull-high resistors. software com register scomc for ht46r065g and ht46r0662g devices, the pins pb0~pb3 on port b can be used as scom lines to drive an external lcd panel. to implement this function, the scomc register is used to setup the correct bias voltages on these pins. oscillator various oscillator options offer the user a wide range of functions according to their various application requirements. the flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. oscillator selections and operation are selected through a combination of configuration options and registers. system oscillator overview in addition to being the source of the main system clock the oscillators also provide clock sources for the watchdog timer and time base functions. external oscillators requiring some external components as well as a two fully integrated internal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. type name freq. pins external crystal hxt 400khz~12mhz osc1/osc2 external rc erc 400khz~12mhz osc1 internal high speed rc hirc 4, 8 or 12mhz external low speed crystal lxt 32768hz osc3/osc4 internal low speed rc lirc 13khz * for ht46r0662g only HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 33 march 3, 2011
system clock configurations there are four system oscillators implemented in this device, three high speed oscillators and one low speed oscillator. the high speed oscillators are the external crystal/ceramic oscillator -- hxt, the external rc oscillator -- erc and the internal rc oscillator -- hirc. the low speed oscillator is the external 32.768khz crystal oscillator -- lxt. the lxt oscillator can be used as the system oscillator only when the hirc oscillator is selected as the high speed system oscillator for the ht46r0662g device. also there is an internal 13khz rc oscillator named lirc oscillator used as the clock source for the wdt function. more details are described in the accompanying sections. external crystal/resonator oscillator hxt the simple connection of a crystal across osc1 and osc2 will create the necessary phase shift and feedback for oscillation. however, for some crystals and most resonator types, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, c1 and c2. the exact values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturer s specification. crystal oscillator c1 and c2 values crystal frequency c1 c2 12mhz 8mhz 4mhz 1mhz 100pf 100pf note: c1 and c2 values are for guidance only. crystal recommended capacitor values rev. 1.00 34 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa / - %
7 " # " $ % & ' $ $ # ( ' & ) ' # / - 3 @ / : 7 7 7 7 7 e : 7 / 7 7 - 7 7 e : - : 7 $ 7 7 " 7 / & - 7 7 + 7 7 7 7 7 7 7 % 7 7 0 * : crystal/resonator oscillator hxt
external rc oscillator erc using the erc oscillator only requires that a resistor, with a value between 24k
and 1.5m
,is connected between osc1 and vdd, and a capacitor is connected between osc and ground, providing a low cost oscillator configuration. it is only the external resistor that determines the oscillation frequency; the external capacitor has no influence over the frequency and is connected for stability purposes only. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. here only the osc1 pin is used, which is shared with i/o pin pa6, leaving pin pa5 free for use as a normal i/o pin. internal rc oscillator hirc the internal rc oscillator is a fully integrated system oscillator requiring no external components. the internal rc oscillator has three fixed frequencies of either 4mhz, 8mhz or 12mhz. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. refer to the a.c. characteristics for more frequency accuracy details. note that if this internal system clock option is selected, as it requires no external pins for its operation, i/o pins pa5 and pa6 are free for use as normal i/o pins or the lxt oscillator pins depending upon the selected device. HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 35 march 3, 2011 ' $ . & / 5 0 4 * # ) ) ' $ , & - external rc oscillator erc ' $ , & ' $ . 7 7 7 7 & 3 @ 7 ' $ , & - ' $ . & / internal rc oscillator hirc
external 32768hz crystal oscillator lxt when the microcontroller enters the idle/sleep mode, the system clock is switched off to stop microcontroller activity and to conserve power. however, in many microcontroller applications it may be necessary to keep the internal timers operational even when the microcontroller is in the power-down mode. to do this, another clock, independent of the system clock, must be provided. to do this a configuration option exists to allow a high speed oscillator to be used in conjunction with a low speed oscillator, known as the lxt oscillator. the lxt oscillator is implemented using a 32768hz crystal connected to pins osc1/osc2 for the HT46R064G / ht46r065g or connected to pins osc3/osc4 for the ht46r0662g. however, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, c1 and c2. the exact values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturers specification. the external parallel feedback resistor, rp, is required. for the HT46R064G/ht46r065g devices the lxt oscillator must be used together with the hirc oscillator. for the ht46r0662g device the lxt oscillator must be used together with the hxt, erc or hirc register. lxt oscillator c1 and c2 values crystal frequency c1 c2 32768hz 10pf 10pf note: 1. c1 and c2 values are for guidance only. 2. r p =5m~10m
is recommended. 32768 hz crystal recommended capacitor values for the ht46r0662g device, a configuration option determines if the osc3/osc4 pins are used for the lxt oscillator or as i/o pins. if the i/o option is selected then the osc3/osc4 pins can be used as normal i/o pins. if the lxt oscillator is selected, then the 32.768 khz crystal should be connected to the osc3/osc4 pins. lxt oscillator low power function the lxt oscillator can function in one of two modes, the quick start mode and the low power mode. the mode selection is executed using the lxtlp bit in the ctrl0 register. lxtlp bit lxt mode 0 quick start 1 low-power rev. 1.00 36 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa
7 " # " $ % & ' $ $ # ( ' & ) ' # / - 3 @ / : 7 a 7 / 7 7 - 7 7 e : - : 7 $ 7 7 " 7 7 + 7 7 7 7 7 7 7 % 7 7 0 * : 7 6 - 0 . b f external lxt oscillator lxt
after power on the lxtlp bit will be automatically cleared to zero ensuring that the lxt oscillator is in the quick start operating mode. in the quick start mode the lxt oscillator will power up and stabilise quickly. however, after the lxt oscillator has fully powered up it can be placed into the low-power mode by setting the lxtlp bit high. the oscillator will continue to run but with re - duced current consumption, as the higher current consumption is only required during the lxt oscil - lator start-up. in power sensitive applications, such as battery applications, where power consumption must be kept to a minimum, it is therefore recommended that the application program sets the lxtlp bit high about 2 seconds after power-on. it should be noted that, no matter what condition the lxtlp bit is set to, the lxt oscillator will always function normally, the only difference is that it will take more time to start up if in the low-power mode. internal low speed oscillator lirc the lirc is a fully self-contained free running on-chip rc oscillator with a typical frequency of 13khz at 5v requiring no external components. when the device enters the idle/sleep mode, the system clock will stop running but the lirc oscillator continues to free-run and to keep the watchdog active. however, to preserve power in certain applications the lirc can be disabled via a configuration option. operating modes by using the lxt low frequency oscillator in combination with a high frequency oscillator, the system can be selected to operate in a number of different modes. these modes are normal, slow, idle and sleep. mode types and selection HT46R064G/ht46r065g for these devices, if the lxt oscillator is used then the internal rc oscillator, hirc, must be used as the high frequency oscillator. if the hxt or the erc oscillator is chosen as the high frequency system clock then the lxt oscillator cannot be used as they share the same oscillator pins. the clkmod bit in the ctrl0 register can be used to switch the system clock from the high speed hirc oscillator to the low speed lxt oscillator. when the halt instruction is executed and the device enters the idle/sleep mode the lxt oscillator will always continue to run. for these devices the lxt crystal is connected to the osc1/osc2 pins and lxt will always run (the lxten bit is not used). note that clkmod is only valid in hirc+lxt oscillator configuration for HT46R064G/ht46r065g. ht46r0662g for the device the lxt oscillator can run together with any of the high speed oscillators, namely the hxt, erc or the hirc. the clkmod bit in the ctrl0 register can be used to switch the system clock from the selected high speed oscillator to the low speed lxt oscillator. when the halt instruction is executed the lxt oscillator can be chosen to run or not using the lxten bit in the ctrl2 register. HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 37 march 3, 2011
note that clkmod is only valid in hirc+lxt oscillator configuration. for all devices, when the system enters the sleep or idle mode, the high frequency system clock will always stop running. the accompanying tables shows the relationship between the clkmod bit, the halt instruction and the high/low frequency oscillators. the clmod bit can change normal or slow mode. operating mode control HT46R064G/ht46r065g operating mode osc1/osc2 configuration hxt erc hirc hirc + lxt hirc lxt normal run run run run run slow stop run sleep stop stop stop stop run unimplemented ht46r0662g operating mode osc1/osc2 configuration osc3/osc4 configuration hxt erc hirc lxt lxten=0 lxten=1 normal run run run run run slow stop stop stop run run idle stop stop stop stop run sleep stop stop stop stop stop rev. 1.00 38 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa b 9
b 9 % 7 ! 9
9 ; ! < ; 3 < ! 9
7 " 7 % b 9
% % b % ! 9
% ! % ? % ? & 5 ! g ) ; ) 7 3 & " 7 < % 7 system clock configurations
mode switching the devices are switched between one mode and another using a combination of the clkmod bit in the ctrl0 register and the halt instruction. the clkmod bit chooses whether the system runs in either the normal or slow mode by selecting the system clock to be sourced from either a high or low frequency oscillator. the halt instruction forces the system into either the idle or sleep mode, depending upon whether the lxt oscillator is running or not. the halt instruction operates independently of the clkmod bit condition. when a halt instruction is executed and the lxt oscillator is not running, the system enters the sleep mode the following conditions exist: the system oscillator will stop running and the application program will stop at the halt instruction. the data memory contents and registers will maintain their present condition. the wdt will be cleared and resume counting if the wdt clock source is selected to come from the lirc or lxt oscillator. the wdt will stop if its clock source originates from the system clock. the i/o ports will maintain their present condition. in the status register, the power down flag, pdf, will be set and the watchdog time-out flag, to, will be cleared. standby current considerations as the main reason for entering the idle/sleep mode is to keep the current consumption of the mcu to as low a value as possible, perhaps only in the order of several micro-amps, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. special attention must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. if the configuration options have enabled the lirc oscillator, then this will continue to run when in the idle/sleep mode and will thus consume some power. for power sensitive applications it may be therefore preferable to use the system clock source for the watchdog timer. the lxt, if configured for use, will also consume a limited amount of power, as it continues to run when the device enters the idle/sleep mode. to keep the lxt power consumption to a minimum level the lxtlp bit in the ctrl0 register, which controls the low power function, should be set high. HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 39 march 3, 2011
wake-up after the system enters the idle/sleep mode, it can be woken up from one of various sources listed as follows: an external reset an external falling edge on pa0~pa7 or pc0~pc7 (ht46r0662g only) a system interrupt a wdt overflow if the system is woken up by an external reset, the device will experience a full system reset, how - ever, if the device is woken up by a wdt overflow, a watchdog timer reset will be initiated. al - though both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the to and pdf flags. the pdf flag is cleared by a sys - tem power-up or executing the clear watchdog timer instructions and is set when executing the halt instruction. the to flag is set if a wdt time-out occurs, and causes a wake-up that only re - sets the program counter and stack pointer, the other flags remain in their original status. pins pa0 to pa7 or pc0 to pc7 can be setup via the pawk or pcwk register to permit a negative transition on the pin to wake-up the system. when a pin on pa0~pa7 or pc0~pc7 wake-up occurs, the program will resume execution at the instruction following the halt instruction. if the system is woken up by an interrupt, then two possible situations may occur. the first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the halt instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request flag is set to 1 before entering the idle/sleep mode, then any future interrupt requests will not generate a wake-up function and the related interrupt will be ignored. no matter what the source of the wake-up event is, once a wake-up event occurs, there will be a time delay before normal program execution resumes. consult the table for the related time. wake-up source oscillator type erc, irc crystal external res t rsdt +t sst1 t rsdt +t sst2 pa or pc* port t sst1 t sst2 interrupt wdt overflow * port c pin wake-up is only available for the ht46r0662g device. note: 1. t rstd (reset delay time), t sys (system clock) 2. t rstd is power-on delay, typical time=50ms 3. t sst1 =2t sys 4. t sst2 = 128 t sys wake-up delay time rev. 1.00 40 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa
watchdog timer the watchdog timer, also known as the wdt, is provided to inhibit program malfunctions caused by the program jumping to unknown locations due to certain uncontrollable external events such as electrical noise. watchdog timer operation it operates by providing a device reset when the watchdog timer counter overflows. note that if the watchdog timer function is not enabled, then any instructions related to the watchdog timer will result in no operation. setting up the various watchdog timer options are controlled via the configuration options and two internal registers wdts and ctrl1. enabling the watchdog timer can be controlled by both a configuration option and the wdten bits in the ctrl1 internal register in the data memory. configuration option ctrl1 register wdt function disable disable off disable enable on enable x on watchdog timer on/off control the watchdog timer will be disabled if bits wdten3~wdten0 in the ctrl1 register are written with the binary value 1010b and wdt configuration option is disable. this will be the condition when the device is powered up. although any other data written to wdten3~wdten0 will ensure that the watchdog timer is enabled, for maximum protection it is recommended that the value 0101b is written to these bits. the watchdog timer clock can emanate from three different sources, selected by configuration option. these are lxt, f sys /4, or lirc. it is important to note that when the system enters the idle/sleep mode the instruction clock is stopped, therefore if the configuration options have selected f sys /4 as the watchdog timer clock source, the watchdog timer will cease to function. for systems that operate in noisy environments, using the lirc or the lxt as the clock source is therefore the recommended choice. the division ratio of the prescaler is determined by bits 0, 1 and 2 of the wdts register, known as ws0, ws1 and ws2. if the watchdog timer internal clock source is selected and with the ws0, ws1 and ws2 bits of the wdts register all set high, the prescaler division ratio will give a maximum time-out period. HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 41 march 3, 2011 / , 7 7 )
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under normal program operation, a watchdog timer time-out will initialise a device reset and set the status bit to. however, if the system is in the idle/sleep mode, when a watchdog timer time-out occurs, the device will be woken up, the to bit in the status register will be set and only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the watchdog timer. the first is an external hardware reset, which means a low level on the external reset pin, the second is using the clear watchdog timer software instructions and the third is when a halt instruction is executed. there are two methods of using software instructions to clear the watchdog timer, one of which must be chosen by configuration option. the first option is to use the single clr wdt instruction while the second is to use the two commands clr wdt1 and clr wdt2 . for the first option, a simple execution of clr wdt will clear the watchdog timer while for the second option, both clr wdt1 and clr wdt2 must both be executed to successfully clear the watchdog timer. note that for this second option, if clr wdt1 is used to clear the watchdog timer, successive executions of this instruction will have no effect, only the execution of a clr wdt2 instruction will clear the watchdog timer. similarly after the clr wdt2 instruction has been executed, only a successive clr wdt1 instruction can clear the watchdog timer. wdts register b i t76543210 name ws2 ws1 ws0 r/w r/w r/w r/w por 111 bit 7~3 : unimplemented, read as 0 bit 2~0 ws2, ws1, ws0 : wdt time-out period selection 000: 2 8 t wdtck 001: 2 9 t wdtck 010: 2 10 t wdtck 011: 2 11 t wdtck 100: 2 12 t wdtck 101: 2 13 t wdtck 110: 2 14 t wdtck 111: 2 15 t wdtck rev. 1.00 42 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa
reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is first applied to the microcontroller. in this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the first program instruction. after this power-on reset, certain important internal registers will be set to defined states before the program commences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. in addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. one example of this is where after power has been applied and the microcontroller is already running, the res line is forcefully pulled low. in such a case, known as a normal operation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. another type of reset is when the watchdog timer overflows and resets the microcontroller. all types of reset operations result in different register conditions being setup. another reset exists in the form of a low voltage reset, lvr, where a full reset, similar to the res reset is implemented in situations where the power supply voltage falls below a certain threshold. reset functions there are five ways in which a microcontroller reset can occur, through events occurring both internally and externally: power-on reset the most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. as well as ensuring that the program memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. although the microcontroller has an internal rc reset function, if the vdd power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. for this reason it is recommended that an external rc network is connected to the res pin, whose additional time delay will ensure that the res pin remains low for an extended period to allow the power supply to stabilise. during this time delay, normal operation of the microcontroller will be inhibited. after the res line reaches a certain voltage value, the reset delay time t rstd is invoked to provide an extra delay time after which the microcontroller will begin normal operation. the abbreviation sst in the figures stands for system start-up timer. HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 43 march 3, 2011 # ) ) 7 4 : 8 7 # ) )
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note: t rstd is power-on delay, typical time=50ms power-on reset timing chart
for most applications a resistor connected between vdd and the res pin and a capacitor connected between vss and the res pin will provide a suitable external reset circuit. any wiring connected to the res pin should be kept as short as possible to minimise any stray noise interference. for applications that operate within an environment where more noise is present the reset circuit shown is recommended. more information regarding external reset circuits is located in application note ha0075e on the holtek website. res pin reset this type of reset occurs when the microcontroller is already running and the res pin is forcefully pulled low by external hardware such as an external switch. in this case as in the case of other reset, the program counter will reset to zero and program execution initiated from this point. rev. 1.00 44 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa 7 4 : 8 7 # ) ) 4 : 5 7 # ) )
) 7 = 7
note: t rstd is power-on delay, typical time=50ms res reset timing chart & ' $ 0 4 : / c / * / 4 > c / 4 4 > # ) ) # 4 : 4 / * h h # ) ) / 3 5 / 5 h 6 4 4 h note: * it is recommended that this component is added for added esd protection ** it is recommended that this component is added in environments where power line noise is significant external res circuit
low voltage reset lvr the microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. the lvr function is selected via a configuration option. if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the battery, the lvr will automatically reset the device internally. for a valid lvr signal, a low supply voltage, i.e., a voltage in the range between 0.9v~v lvr must exist for a time greater than that specified by t lvr in the a.c. characteristics. if the low supply voltage state does not exceed this value, the lvr will ignore the low supply voltage and will not perform a reset function. the actual v lvr value can be selected via configuration options. watchdog time-out reset during normal operation the watchdog time-out reset during normal operation is the same as a hardware res pin reset except that the watchdog time-out flag to will be set to 1 . watchdog time-out reset during idle/sleep mode the watchdog time-out reset during idle/sleep mode is a little different from other kinds of reset. most of the conditions remain unchanged except that the program counter and the stack pointer will be cleared to 0 and the to flag will be set to 1 . refer to the a.c. characteristics for t sst details. note: the t sst can be chosen to be either 128 or 2 clock cycles via configuration option if the system clock source is provided by erc or hirc. the sst is 128 for hxt or lxt. HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 45 march 3, 2011
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7
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note: t rstd is power-on delay, typical time=50ms low voltage reset timing chart
reset initial conditions the different types of reset described affect the reset flags in different ways. these flags, known as pdf and to are located in the status register and are controlled by various microcontroller operations, such as the idle/sleep function or watchdog timer. the reset flags are shown in the table: to pdf reset conditions 0 0 power-on reset u u res or lvr reset during normal or slow mode operation 1 u wdt time-out reset during normal or slow mode operation 1 1 wdt time-out reset during idle or sleep mode operation note: u stands for unchanged the following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. item condition after reset program counter reset to zero interrupts all interrupts will be disabled wdt clear after reset, wdt begins counting timer/event counter timer counter will be turned off prescaler the timer counter prescaler will be cleared input/output ports i/o ports will be setup as inputs stack pointer stack pointer will point to the top of the stack the different kinds of resets all affect the internal registers of the microcontroller in different ways. to ensure reliable continuation of normal program executio n after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table de- scribes how each type of reset affects each of the microcontroller internal registers. register power-on reset res or lvr reset wdt time-out (normal operation) wdt time-out (idle/sleep) pcl 0000 0000 0000 0000 0000 0000 0000 0000 mp0 1xxx xxxx 1xxx xxxx 1xxx xxxx 1uuu uuuu xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu mp1 1xxx xxxx 1xxx xxxx 1xxx xxxx 1uuu uuuu xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu bp 0 0 0 u acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblh xx xxxx uu uuuu uu uuuu uu uuuu xxx xxxx uuu uuuu uuu uuuu uuu uuuu wdts 111 111 111 uuu rev. 1.00 46 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa ht46r065g HT46R064G ht46r0662g
register power-on reset res or lvr reset wdt time-out (normal operation) wdt time-out (idle/sleep) status 00 xxxx uu uuuu 1u uuuu 11 uuuu intc0 00 000 00 000 00 000 uu uuu 000 0000 000 0000 000 0000 uuu uuuu intc1 000 000 000 000 000 000 uuu uuu mfic 000 000 000 000 000 000 uuu uuu tmr0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr0c 0000 1000 0000 1000 0000 1000 uuuu uuuu tmr1 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr1c 0000 1 0000 1 0000 1 uuuu u pa 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 uuuu uuuu pawk 0000 0000 0000 0000 0000 0000 uuuu uuuu papu 000 0000 000 0000 000 0000 uuu uuuu pb 1111 1111 1111 uuuu 11 1111 11 1111 11 1111 uu uuuu 1111 1111 1111 1111 1111 1111 uuuu uuuu pbc 1111 1111 1111 uuuu 11 1111 11 1111 11 1111 uu uuuu 1111 1111 1111 1111 1111 1111 uuuu uuuu pbpu 0000 0000 0000 uuuu 00 0000 00 0000 00 0000 uu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu pc 1111 11 1111 11 1111 11 uuuu uu 1111 1111 1111 1111 1111 1111 uuuu uuuu pcc 1111 11 1111 11 1111 11 uuuu uu 1111 1111 1111 1111 1111 1111 uuuu uuuu pcpu 0000 00 0000 00 0000 00 uuuu uu 0000 0000 0000 0000 0000 0000 uuuu uuuu pcwk 0000 0000 0000 0000 0000 0000 uuuu uuuu pd 1111 1111 1111 1111 1111 1111 uuuu uuuu pdc 1111 1111 1111 1111 1111 1111 uuuu uuuu pdpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pe 1111 1111 1111 1111 1111 1111 uuuu uuuu pec 1111 1111 1111 1111 1111 1111 uuuu uuuu HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 47 march 3, 2011 ht46r065g HT46R064G ht46r0662g
register power-on reset res or lvr reset wdt time-out (normal operation) wdt time-out (idle/sleep) pepu 0000 0000 0000 0000 0000 0000 uuuu uuuu pf 11 11 11 uu pfc 11 11 11 uu pfpu 00 00 00 uu ctrl0 0 0000 0 0000 0 0000 u uuuu 00 0000 00 0000 00 0000 uu uuuu 000 0000 000 0000 000 0000 uuu uuuu ctrl1 1000 1010 1000 1010 1000 1010 uuuu uuuu ctrl2 00 100 100 1uu u scomc 0000 0000 0000 0000 0000 0000 uuuu uuuu pwm0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu pwm1 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adrl xxxx xxxx xxxx uuuu adrh xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adcr 01 000 01 000 01 000 uu uuu acsr 1 00 1 00 1 00 1 uu 11 0 000 11 0 000 11 0 000 uu u uuu pcr 00 00 00 uu 0000 0000 0000 uuuu ancsr0 0000 0000 0000 0000 0000 0000 uuuu uuuu cmp0c 000 0000 000 0000 000 0000 uuu uuuu cmp1c 000 0 00 000 0 00 000 0 00 uuu u uu copa0c 0000 0000 0000 0000 0000 0000 uuuu uuuu copa1c 0000 0000 0000 0000 0000 0000 uuuu uuuu copa2c 0000 0000 0000 0000 0000 0000 uuuu uuuu copa3c 0000 0000 0000 0000 0000 0000 uuuu uuuu opa0oc 0x00 1000 0x00 1000 0x00 1000 uuuu uuuu opa1oc 0x00 1000 0x00 1000 0x00 1000 uuuu uuuu note: - not implemented u means unchanged x means unknown rev. 1.00 48 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa ht46r065g HT46R064G ht46r0662g
input/output ports holtek microcontrollers offer considerable flexibility on their i/o ports. most pins can have either an input or output designation under user program control. additionally, as there are pull-high resistors and wake-up software configurations, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. for input operation, these ports are non-latching, which means the inputs must be ready at the t2 rising edge of instruction mov a,[m] , where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. to eliminate the need for these external resistors, when configured as an input have the capability of being connected to an internal pull-high resistor. these pull-high resistors are selectable via a register known as papu, pbpu, pcpu, pdpu, pepu and pfpu located in the data memory. the pull-high resistors are implemented using weak pmos transistors. note that pin pa7 does not have a pull-high resistor selection. i/o port wake-up if the halt instruction is executed, the device will enter the idle/sleep mode, where the system clock will stop resulting in power being conserved, a feature that is important for battery and other low-power applications. various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the pa0~pa7 pins from high to low. for the ht46r0662g device, a logic transition from high to low on one of the pc0~pc7 pins can also wake up the microcontroller if the corresponding wake-up function control is enabled. after a halt instruction forces the microcontroller into entering the idle/sleep mode, the processor will remain idle or in a low-power state until the logic condition of the selected wake-up pin on port a or port c changes from high to low. this function is especially suitable for applications that can be woken up via external switches. note that pins pa0~pa7 or pc0~pc7 can be selected individually to have this wake-up feature using an internal register known as pawk or pcwk, located in the data memory. pawk, pac~pcc, papu~pcpu registers HT46R064G register name por bit 76543210 pawk 00h pawk7 pawk6 pawk5 pawk4 pawk3 pawk2 pawk1 pawk0 pac ffh pac7 pac6 pac5 pac4 pac3 pac2 pac1 pac0 papu 00h papu6 papu5 papu4 papu3 papu2 papu1 papu0 pbc 0fh pbc3 pbc2 pbc1 pbc0 pbpu 00h pbpu3 pbpu2 pbpu1 pbpu0 pcc f3h pcc7 pcc6 pcc5 pcc4 pcc1 pcc0 pcpu 00h pcpu7 pcpu6 pcpu5 pcpu4 pcpu1 pcpu0 unimplemented, read as 0 pawkn : pa wake-up function enable 0: disable 1: enable pacn/pbcn/pccn : i/o type selection 0: output 1: input papun/pbpun/pcpun : pull-high function enable 0: disable 1: enable HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 49 march 3, 2011
pawk, pac~pcc, papu~pcpu registers ht46r065g register name por bit 76543210 pawk 00h pawk7 pawk6 pawk5 pawk4 pawk3 pawk2 pawk1 pawk0 pac ffh pac7 pac6 pac5 pac4 pac3 pac2 pac1 pac0 papu 00h papu6 papu5 papu4 papu3 papu2 papu1 papu0 pbc 3fh pbc5 pbc4 pbc3 pbc2 pbc1 pbc0 pbpu 00h pbpu5 pbpu4 pbpu3 pbpu2 pbpu1 pbpu0 pcc ffh pcc7 pcc6 pcc5 pcc4 pcc3 pcc2 pcc1 pcc0 pcpu 00h pcpu7 pcpu6 pcpu5 pcpu4 pcpu3 pcpu2 pcpu1 pcpu0 unimplemented, read as 0 pawkn : pa wake-up function enable 0: disable 1: enable pacn/pbcn/pccn : i/o type selection 0: output 1: input papun/pbpun/pcpun : pull-high function enable 0: disable 1: enable pawk, pcwk, pac~pfc, papu~pfpu registers ht46r0662g register name por bit 76543210 pawk 00h pawk7 pawk6 pawk5 pawk4 pawk3 pawk2 pawk1 pawk0 pac ffh pac7 pac6 pac5 pac4 pac3 pac2 pac1 pac0 papu 00h papu6 papu5 papu4 papu3 papu2 papu1 papu0 pbc ffh pbc7 pbc6 pbc5 pbc4 pbc3 pbc2 pbc1 pbc0 pbpu 00h pbpu7 pbpu6 pbpu5 pbpu4 pbpu3 pbpu2 pbpu1 pbpu0 pcwk 00h pcwk7 pcwk6 pcwk5 pcwk4 pcwk3 pcwk2 pcwk1 pcwk0 pcc ffh pcc7 pcc6 pcc5 pcc4 pcc3 pcc2 pcc1 pcc0 pcpu 00h pcpu7 pcpu6 pcpu5 pcpu4 pcpu3 pcpu2 pcpu1 pcpu0 pdc ffh pdc7 pdc6 pdc5 pdc4 pdc3 pdc2 pdc1 pdc0 pdpu 00h pdpu7 pdpu6 pdpu5 pdpu4 pdpu3 pdpu2 pdpu1 pdpu0 pec ffh pec7 pec6 pec5 pec4 pec3 pec2 pec1 pec0 pepu 00h pepu7 pepu6 pepu5 pepu4 pepu3 pepu2 pepu1 pepu0 pfc 03h pfc1 pfc0 pfpu 00h pfpu1 pfpu0 unimplemented, read as 0 pawkn/pcwkn : pa/pc wake-up function enable 0: disable 1: enable pacn/pbcn/pccn/pdcn/pecn/pfcn : i/o type selection 0: output 1: input papun/pbpun/pcpun/pdpun/pepun/pfpun : pull-high function enable 0: disable 1: enable rev. 1.00 50 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa
i/o port control registers each port has its own control register, known as pac, pbc, pcc, pdc, pec, pfc which controls the input/output configuration. with this control register, each i/o pin with or without pull-high resistors can be reconfigured dynamically under software control. for the i/o pin to function as an input, the corresponding bit of the control register must be written as a 1 . this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a 0 , the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register. however, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. pin-shared functions the flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome. for some pins, the chosen function of the multi-function i/o pins is set by configuration options while for others the function is set by application program control. external interrupt input the external interrupt pin, int, is pin-shared with an i/o pin. to use the pin as an external interrupt input the correct bits in the intc register must be programmed. the pin must also be setup as an input by setting the pac3 bit in the port control register. an internal pull-high resistor can be selected to be connected to this pin by the corresponding pull-high function enable control bit. note that even if the pin is setup as an external interrupt input the i/o function still remains. external timer/event counter input the timer/event counter pin tcn is pin-shared with i/o pins. for the shared pin to be used as the timer/event counter input, the timer/event counter n must be configured to be in the event counter or pulse width capture mode. this is achieved by setting the appropriate bits in the timer/event counter control register. the pins must also be setup as inputs by setting the appropriate bit in the port control register. pull-high resistor function for the tcn pin can also be selected using the port pull-high resistor register. note that even if the pin is setup as an external timer input the i/o function still remains. HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 51 march 3, 2011 # ) ) 9 > 7 7 > 7 ) 7 ) i g ) i g 7 ( ) 7 ( 7 7 7 7 7 7 ) 7 ) 7 ( & 7 i i > 7 % 7 7 > ' ' b generic input/output ports
rev. 1.00 52 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa > 7 % 9 7 ) 7 7 ( ) 7 ( 7 7 7 7 7 7 ) 7 ) 7 ( ) i g i ) i g i & 7 > res nmos input/output port # ) ) 9 7 ) 7 7 ( ' b 7 ) 7 ( 7 7 7 7 7 7 ) 7 ) 7 ( ' ( 4 & 4 c ' ( 6 & 6 ' ( 5 c ' ( 0 # ) ) & - > ' ) i g i ) i g i 3 3 pb input/output port
pfd output the pfd function output is pin-shared with an i/o pin. the output function of this pin is chosen using the ctrl0 register. note that the corresponding bit of the port control register, must setup the pin as an output to enable the pfd output. if the port control register has setup the pin as an input, then the pin will function as a normal logic input with the usual pull-high selection, even if the pfd function has been selected. pwm outputs the pwm function whose outputs are pin-shared with i/o pins. the pwm output functions are chosen using the ctrl0 register. note that the corresponding bit of the port control registers, for the output pin, must setup the pin as an output to enable the pwm output. if the pins are setup as inputs, then the pin will function as a normal logic input with the usual pull-high selections, even if the pwm registers have enabled the pwm function. scom driver pins pins pb0~pb3 on port b for the ht46r065g and ht46r0662g devices can be used as lcd com driver pins. this function is controlled using the scomc register which will generate the necessary 1/2 bias signals on these four pins. a/d inputs these devices have up to eight inputs to the a/d converter. all of these analog inputs are pin-shared with i/o pins. if these pins are to be used as a/d inputs and not as i/o pins, then the corresponding pcrn bits in the a/d converter control register, pcr or ancsr, must be properly setup. there are no configuration options associated with the a/d converter. if chosen as i/o pins, then full pull-high resistor control remains, however if used as a/d inputs then any pull-high resistor control associated with these pins will be automatically disconnected. HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 53 march 3, 2011 # ) ) 9 7 ) 7 7 ( ) 7 ( 7 7 7 7 7 7 ) 7 ) 7 ( $ & ) 7 7 ' $ - c $ 4
7 $ & ) 7 + > ' $ ) i g i ) i g i ' b a/d input/output structure
pin remapping configuration ht46r0662g the pin remapping function for the ht46r0662g device enables the function pins int, tc0, tc1 and pfd to be located on different port pins. it is important not to confuse the pin remapping function with the pin-shared function; these two functions have no interdependence. the pcfg1 and pcfg0 bits in the ctrl2 register allow the four function pins int, tc0, tc1 and pfd to be remapped to different port pins. after power up, this bit will be reset to zero, which will define the default port pins to which these functions will be mapped. changing these bits will move the functions to other port pins. examination of the pin names on the package diagrams will reveal that some pin function names are repeated, this indicates a function pin that can be remapped to other port pins. if the pin name is bracketed, then this indicates its alternative location. pin name without brackets indicates its default location which is the condition after power-on. pcfg [1:0] bits status pcfg [1:0] bit 00 01 10 11 pin mapping pfd/pa1 tc0/pa2 int/pa3 tc1/pa4 pfd/pc5 tc0/pc4 int/pc3 tc1/pc2 pfd/pb0 tc0/pb1 int/pb2 tc1/pb3 pfd/pe0 tc0/pe1 int/pe2 tc1/pe3 pin remapping i/o pin structures the diagrams illustrate the i/o pin internal structures. as the exact logical construction of the i/o pin may differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. programming considerations within the user program, one of the first things to consider is port initialisation. after a reset, the i/o data register and i/o port control register will be set high. this means that all i/o pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high options have been selected. if the port control registers, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data register is first programmed. selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct value into the port control register or by programming individual bits in the port control register using the set [m].i and clr [m].i instructions. note that when using these bit control instructions, a read-modify-write operation takes place. the microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. pins on pa0 to pa7 for all the devices or pc0 to pc7 for only the ht46r0662g device each have a wake-up function, selected via the pawk or pcwk register. when the device is in the idle/sleep mode, various methods are available to wake the device up. one of these is a high to low transition of any of these pins. single or multiple pins on port a or port c can be setup to have this function. rev. 1.00 54 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa
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timer/event counters the provision of timers form an important part of any microcontroller, giving the designer a means of carrying out time related functions. the devices contain from one to three count-up timer of 8-bit capacity. as the timers have three different operating modes, they can be configured to operate as a general timer, an external event counter or as a pulse width capture device. the provision of an internal prescaler to the clock circuitry on gives added range to the timers. there are two types of registers related to the timer/event counters. the first is the register that contains the actual value of the timer and into which an initial value can be preloaded. reading from this register retrieves the contents of the timer/event counter. the second type of associated register is the timer control register which defines the timer options and determines how the timer is to be used. the device can have the timer clock configured to come from the internal clock source. in addition, the timer clock source can also be configured to come from an external timer pin. configuring the timer/event counter input clock source the timer/event counter clock source can originate from various sources, an internal clock or an external pin. the internal clock source is used when the timer is in the timer mode or in the pulse width capture mode. for the timer/event counter 0, this internal clock source is first divided by a prescaler, the division ratio of which is conditioned by the timer control register bits t0psc0~t0psc2. the internal clock source can be derived from the system clock f sys or the lxt oscillator for timer/event counter 0 or from the instruction clock f sys /4 or the lxt oscillator for timer/event counter 1 selected by the clock selection bit tns in the control register tmrnc. an external clock source is used when the timer/event counter is in the event counting mode, the clock source being provided on an external timer pin tcn. depending upon the condition of the tneg bit, each high to low, or low to high transition on the external timer pin will increment the counter by one. timer registers tmr0, tmr1 the timer register is a special function register located in the special purpose data memory and is the place where the actual timer value is stored and the register is known as tmrn. the value in the timer register increases by one each time an internal clock pulse is received or an external transition occurs on the external timer pin. the timer will count from the initial value loaded by the preload register to the full count of ffh at which point the timer overflows and an internal interrupt signal is generated. the timer value will be reset with the initial preload register value and continue counting. to achieve a maximum full range count of ffh, the preload register must first be cleared to all zeros. it should be noted that after power-on, the preload register will be in an unknown condition. note that if the timer/event counter is switched off and data is written to its preload register, this data will be immediately written into the actual timer register. however, if the timer/event counter is enabled and counting, any new data written into the preload data register during this period will remain in the preload register and will only be written into the timer register the next time an overflow occurs. HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 55 march 3, 2011
rev. 1.00 56 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa
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' & / - < / 7 9 0 0 clock structure for timer/pwm/time base 9 ' * ) 7 ' * ) 4 4 / ' * ) / ' * ) ht46r0662g pfd clock source note: if pwm0/pwm1 is enabled, then f tp comes from f sys and the t0s bit will have no effect.
timer control registers tmr0c, tmr1c the flexible features of the holtek microcontroller timer/event counters enable them to operate in three different modes, the options of which are determined by the contents of their respective control register. the timer control register is known as tmrnc. it is the timer control register together with its corresponding timer register that control the full operation of the timer/event counter. before the timer can be used, it is essential that the timer control register is fully programmed with the right data to ensure its correct operation, a process that is normally carried out during program initialisation. to choose which of the three modes the timer is to operate in, either in the timer mode, the event counting mode or the pulse width capture mode, bits 7 and 6 of the timer control register, which are known as the bit pair tnm1/tnm0, must be set to the required logic levels. the timer-on bit, which is bit 4 of the timer control register and known as tnon, provides the basic on/off control of the respective timer. setting the bit high allows the counter to run, clearing the bit stops the counter. bits 0~2 of the timer control register determine the division ratio of the input clock prescaler. the prescaler bit settings have no effect if an external clock source is used. if the timer is in the event count or pulse width capture mode, the active transition edge level type is selected by the logic level of bit 3 of the timer control register which is known as tneg. the tns bit selects the internal clock source if used. tmr0c register bit76543210 name t0m1 t0m0 t0s t0on t0eg t0psc2 t0psc1 t0psc0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00001000 bit 7,6 t0m1, t0m0 : timer0 operation mode selection 00: no mode available 01: event counter mode 10: timer mode 11: pulse width capture mode bit 5 t0s : timer clock source 0: f sys 1: lxt oscillator t0s selects the clock source for f tp which is provided for timer 0, the time-base and the pwm. if the pwm is enabled, then f sys will be selected, overriding the t0s selection. bit 4 t0on : timer/event counter counting enable 0: disable 1: enable bit 3 t0eg: event counter active edge selection 0: count on raising edge 1: count on falling edge pulse width capture active edge selection 0: start counting on falling edge, stop on rasing edge 1: start counting on raising edge, stop on falling edge bit 2~0 t0psc2, t0psc1, t0psc0 : timer prescaler rate selection timer internal clock= 000: f tp 001: f tp /2 010: f tp /4 011: f tp /8 100: f tp /16 101: f tp /32 110: f tp /64 111: f tp /128 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 57 march 3, 2011
tmr1c register bit76543210 name t1m1 t1m0 t1s t1on t1eg r/w r/w r/w r/w r/w r/w por00001 bit 7,6 t1m1, t1m0 : timer 1 operation mode selection 00: no mode available 01: event counter mode 10: timer mode 11: pulse width capture mode bit 5 t1s : timer clock source 0: f sys /4 1: lxt oscillator bit 4 t1on : timer/event counter counting enable 0: disable 1: enable bit 3 t1eg: event counter active edge selection 0: count on raising edge 1: count on falling edge pulse width capture active edge selection 0: start counting on falling edge, stop on rasing edge 1: start counting on raising edge, stop on falling edge bit 2~0 unimplemented, read as 0 timer mode in this mode, the timer/event counter can be utilised to measure fixed time intervals, providing an internal interrupt signal each time the timer/event counter overflows. to operate in this mode, the operating mode select bit pair, tnm1/tnm0, in the timer control register must be set to the correct value as shown. control register operating mode select bits for the timer mode bit7 bit6 10 in this mode the internal clock is used as the timer clock. the timer input clock source is f sys ,f sys /4 or the lxt oscillator depending upon whether the timer/event counter 0 or timer/event counter 1 is selected. for timer/event counter 0, the timer clock source is further divided by a prescaler, the value of which is determined by the bits t0psc2~t0psc0 in the timer control register tmr0c. the timer-on bit, tnon must be set high to enable the timer to run. each time an internal clock high to low transition occurs, the timer increments by one; when the timer is full and overflows, an interrupt signal is generated and the timer will reload the value already loaded into the preload register and continue counting. a timer overflow condition and corresponding internal interrupt is one of the wake-up sources, however, the internal interrupts can be disabled by ensuring that the tne bits of the intc0 register are reset to zero. rev. 1.00 58 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa
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event counter mode in this mode, a number of externally changing logic events, occurring on the external timer tcn pin, can be recorded by the timer/event counter. to operate in this mode, the operating mode select bit pair, tnm1/tnm0, in the timer control register must be set to the correct value as shown. control register operating mode select bits for the event counter mode bit7 bit6 01 in this mode, the external timer tcn pin, is used as the timer/event counter clock source, however it is not divided by the internal prescaler. after the other bits in the timer control register have been setup, the enable bit tnon, which is bit 4 of the timer control register, can be set high to enable the timer/event counter to run. if the active edge select bit, tneg, which is bit 3 of the timer control register, is low, the timer/event counter will increment each time the external timer pin receives a low to high transition. if the tneg is high, the counter will increment each time the external timer pin receives a high to low transition. when it is full and overflows, an interrupt signal is generated and the timer/event counter will reload the value already loaded into the preload register and continue counting. the interrupt can be disabled by ensuring that the timer/event counter interrupt enable bit in the corresponding interrupt control register, is reset to zero. as the external timer pin is shared with an i/o pin, to ensure that the pin is configured to operate as an event counter input pin, two things have to happen. the first is to ensure that the operating mode select bits in the timer control register place the timer/event counter in the event counting mode, the second is to ensure that the port control register configures the pin as an input. it should be noted that in the event counting mode, even if the microcontroller is in the idle/sleep mode, the timer/event counter will continue to record externally changing logic events on the timer input tcn pin. as a result when the timer overflows it will generate a timer interrupt and corresponding wake-up source. pulse width capture mode in this mode, the timer/event counter can be utilised to measure the width of external pulses applied to the external timer pin. to operate in this mode, the operating mode select bit pair, tnm1/tnm0, in the timer control register must be set to the correct value as shown. control register operating mode select bits for the pulse width capture mode bit7 bit6 11 in this mode the internal clock, f sys ,f sys /4 or the lxt oscillator, is used as the internal clock determined by which timer/event counter is selected to be used. the internal clock source for the timer/event counter 0 is further divided by a prescaler, the value of which is determined by the prescaler rate select bits named t0psc2~t0psc0, which are bits 2~0 in the timer control register. after other bits in the timer control register have been setup, the enable bit tnon, which is bit 4 of the timer control register, can be set high to enable the timer/event counter, however it will not actually start counting until an active edge is received on the external timer pin. if the active edge select bit tneg, which is bit 3 of the timer control register, is low, once a high to low transition has been received on the external timer pin, the timer/event counter will start counting until the external timer pin returns to its original high level. at this point the enable bit will be automatically reset to zero and the timer/event counter will stop counting. if the active edge select bit is high, the timer/event counter will begin counting once a low to high transition has been received on the external timer pin and stop counting when the external timer pin returns to its original HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 59 march 3, 2011
event counter mode timing chart (tneg=1)
low level. as before, the enable bit will be automatically reset to zero and the timer/event counter will stop counting. it is important to note that in the pulse width capture mode, the enable bit is automatically reset to zero when the external control signal on the external timer pin returns to its original level, whereas in the other two modes the enable bit can only be reset to zero under program control. the residual value in the timer/event counter, which can now be read by the program, therefore represents the length of the pulse received on the tcn pin. as the enable bit has now been reset, any further transitions on the external timer pin will be ignored. the timer cannot begin further pulse width capture until the enable bit is set high again by the program. in this way, single shot pulse measurements can be easily made. it should be noted that in this mode the timer/event counter is controlled by logical transitions on the external timer pin and not by the logic level. when the timer/event counter is full and overflows, an interrupt signal is generated and the timer/event counter will reload the value already loaded into the preload register and continue counting. the interrupt can be disabled by ensuring that the timer/event counter interrupt enable bit in the corresponding interrupt control register, is reset to zero. as the tcn pin is shared with an i/o pin, to ensure that the pin is configured to operate as a pulse width capture pin, two things have to happen. the first is to ensure that the operating mode select bits in the timer control register place the timer/event counter in the pulse width capture mode, the second is to ensure that the port control register configures the pin as an input. prescaler bits t0psc0~t0psc2 of the tmr0c register can be used to define a division ratio for the internal clock source of the timer/event counter enabling longer time out periods to be setup. pfd function the programmable frequency divider provides a means of producing a variable frequency output suitable for applications, such as piezo-buzzer driving or other interfaces requiring a precise frequency generator. the timer/event counter overflow signal is the clock source for the pfd function, which is controlled by pfdcs bit in ctrl0. for applicable devices the clock source can come from either timer/event counter 0 or timer/event counter 1. the output frequency is controlled by loading the required values into the timer prescaler and timer registers to give the required division ratio. the counter will begin to count-up from this preload register value until full, at which point an overflow signal is generated, causing both the pfd outputs to change state. the counter will then be automatically reloaded with the preload register value and continue counting-up. if the ctrl0 register has selected the pfd function, then for pfd output to operate, it is essential for the corresponding port control register, to setup the pfd pins as outputs. the corresponding i/o pin data bit must be set high to activate the pfd. the output data bits can be used as the on/off control bit for the pfd outputs. note that the pfd outputs will all be low if the output data bit is cleared to zero. rev. 1.00 60 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa = / = - = 6 = 5
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using this method of frequency generation, and if a crystal oscillator is used for the system clock, very precise values of frequency can be generated. i/o interfacing the timer/event counter, when configured to run in the event counter or pulse width capture mode, requires the use of an external timer pin for its operation. as this pin is a shared pin it must be configured correctly to ensure that it is setup for use as a timer/event counter input pin. this is achieved by ensuring that the mode select bits in the timer/event counter control register, select either the event counter or pulse width capture mode. additionally the corresponding port control register bit must be set high to ensure that the pin is setup as an input. any pull-high resistor connected to this pin will remain valid even if the pin is used as a timer/event counter input. programming considerations when configured to run in the timer mode, the internal system clock is used as the timer clock source and is therefore synchronised with the overall operation of the microcontroller. in this mode when the appropriate timer register is full, the microcontroller will generate an internal interrupt signal directing the program flow to the respective internal interrupt vector. for the pulse width capture mode, the internal system clock is also used as the timer clock source but the timer will only run when the correct logic condition appears on the external timer input pin. as this is an external event and not synchronised with the internal timer clock, the microcontroller will only see this external event when the next timer clock pulse arrives. as a result, there may be small differences in measured values requiring programmers to take this into account during programming. the same applies if the timer is configured to be in the event counting mode, which again is an external event and not synchronised with the internal system or timer clock. when the timer/event counter is read, or if data is written to the preload register, the clock is inhibited to avoid errors, however as this may result in a counting error, this should be taken into account by the programmer. care must be taken to ensure that the timers are properly initialised before using them for the first time. the associated timer enable bits in the interrupt control register must be properly set otherwise the internal interrupt associated with the timer will remain inactive. the edge select, timer mode and clock source control bits in timer control register must also be correctly set to ensure the timer is properly configured for the required application. it is also important to ensure that an initial value is first loaded into the timer registers before the timer is switched on; this is because after power-on the initial values of the timer registers are unknown. after the timer has been initialised the timer can be turned on and off by controlling the enable bit in the timer control register. when the timer/event counter overflows, its corresponding interrupt request flag in the interrupt control register will be set. if the timer/event counter interrupt is enabled this will in turn generate an interrupt signal. however irrespective of whether the interrupts are enabled or not, a timer/event counter overflow will also generate a wake-up signal if the device is in a power-down condition. this situation may occur if the timer/event counter is in the event counting mode and if the external signal continues to change state. in such a case, the timer/event counter will continue to count these external events and if an overflow occurs the device will be woken up from its power-down condition. to prevent such a wake-up from occurring, the timer interrupt request flag should first be set high before issuing the halt instruction to enter the idle/sleep mode. HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 61 march 3, 2011
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timer program example the program shows how the timer/event counter registers are setup along with how the interrupts are enabled and managed. note how the timer/event counter is turned on, by setting bit 4 of the timer control register. the timer/event counter can be turned off in a similar way by clearing the same bit. this example program sets the timer/event counters to be in the timer mode, which uses the internal system clock as their clock source. timer programming example org 04h ; external interrupt vector org 08h ; timer counter 0 interrupt vector jmp tmr0int ; jump here when timer 0 overflows :: org 20h ; main program :: ;internal timer 0 interrupt routine tmr0int: : ; timer 0 main program placed here : : begin: ;setup timer 0 registers mov a,09bh ; setup timer 0 preload value mov tmr0,a mov a,081h ; setup timer 0 control register mov tmr0c,a ; timer mode and prescaler set to /2 ;setup interrupt register mov a,00dh ; enable master interrupt and both timer interrupts mov intc0,a :: set tmr0c.4 ; start timer 0 :: time base the device includes a time base function which is used to generate a regular time interval signal. the time base time interval magnitude is determined using an internal 13 stage counter sets the division ratio of the clock source. this division ratio is controlled by both the tbsel0 and tbsel1 bits in the ctrl1 register. the clock source is selected using the t0s bit in the tmr0c register. when the time base time out, a time base interrupt signal will be generated. it should be noted that as the time base clock source is the same as the timer/event counter clock source, care should be taken when programming. rev. 1.00 62 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa
pulse width modulator the series of devices includes up to 2 8-bit pwm outputs. useful for the applications such as motor speed control, the pwm function provides outputs with a fixed frequency but with a duty cycle that can be varied by setting particular values into the corresponding pwm register. device channels mode pins registers HT46R064G ht46r065g 1 6+2 7+1 pa4 pwm0 ht46r0662g 2 pd0 pd1 pwm0 pwm1 pwm operation the register, known as pwmn and located in the data memory, is assigned to each pulse width modulator channel. it is here that the 8-bit value, which represents the overall duty cycle of one modulation cycle of the output waveform, should be placed. to increase the pwm modulation frequency, each modulation cycle is subdivided into two or four individual modulation subsections, known as the 7+1 mode or 6+2 mode respectively. the required mode and the on/off control for each pwm channel is selected using the ctrl0 register. note that when using the pwm, it is only necessary to write the required value into the pwmn register and select the required mode setup and on/off control using the ctrl0 register, the subdivision of the waveform into its sub-modulation cycles is implemented automatically within the microcontroller hardware. the pwm clock source is the system clock f sys . this method of dividing the original modulation cycle into a further 2 or 4 sub-cycles enable the generation of higher pwm frequencies which allow a wider range of applications to be served. the difference between what is known as the pwm cycle frequency and the pwm modulation frequency should be understood. as the pwm clock is the system clock, f sys , and as the pwm value is 8-bits wide, the overall pwm cycle frequency is f sys /256. however, when in the 7+1 mode of operation the pwm modulation frequency will be f sys /128, while the pwm modulation frequency for the 6+2 mode of operation will be f sys /64. pwm modulation pwm cycle frequency pwm cycle duty f sys /64 for (6+2) bits mode f sys /128for (7+1) bits mode f sys /256 [pwm]/256 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 63 march 3, 2011 ' 4 7 7 7 4 ' / 7 7 7 / & ; 0 = / < & ; . = - < ' 7 ' 4 ' / pwm block diagram
6+2 pwm mode each full pwm cycle, as it is controlled by an 8-bit pwm register, has 256 clock periods. however, in the 6+2 pwm mode, each pwm cycle is subdivided into four individual sub-cycles known as modulation cycle 0 ~ modulation cycle 3, denoted as i in the table. each one of these four sub-cycles contains 64 clock cycles. in this mode, a modulation frequency increase of four is achieved. the 8-bit pwm register value, which represents the overall duty cycle of the pwm waveform, is divided into two groups. the first group which consists of bit2~bit7 is denoted here as the dc value. the second group which consists of bit0~bit1 is known as the ac value. in the 6+2 pwm mode, the duty cycle value of each of the four modulation sub-cycles is shown in the following table. parameter ac (0~3) dc (duty cycle) modulation cycle i (i=0~3) iHT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa % ? & - ' 1 ' 2 7 j / 4 4 1 ' 2 7 j / 4 / ' 1 ' 2 7 j / 4 - ' 1 ' 2 7 j / 4 6 ' ' 7 7 @ 7 - , . & % ? - , & . 5 - . & . 5 - . & . 5 - . & . 5 - , & . 5 - , & . 5 - , & . 5 - , & . 5 - , & . 5 - , & . 5 - , & . 5 - . & . 5 - . & . 5 - , & . 5 - , & . 5 - . & . 5 - , & . 5 - . & . 5 - . & . 5 - . & . 5 7 7 4 ' 7 7 7 @ 7 . 5 & % ? 7 7 / 7 7 - 7 7 6 7 7 4 6+2 pwm mode *
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7+1 pwm mode each full pwm cycle, as it is controlled by an 8-bit pwm register, has 256 clock periods. however, in the 7+1 pwm mode, each pwm cycle is subdivided into two individual sub-cycles known as modulation cycle 0 ~ modulation cycle 1, denoted as i in the table. each one of these two sub-cycles contains 128 clock cycles. in this mode, a modulation frequency increase of two is achieved. the 8-bit pwm register value, which represents the overall duty cycle of the pwm waveform, is divided into two groups. the first group which consists of bit1~bit7 is denoted here as the dc value. the second group which consists of bit0 is known as the ac value. in the 7+1 pwm mode, the duty cycle value of each of the two modulation sub-cycles is shown in the following table. parameter ac (0~1) dc (duty cycle) modulation cycle i (i=0~1) iHT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 65 march 3, 2011 % ? & - ' 1 ' 2 7 j / 4 4 1 ' 2 7 j / 4 / ' 1 ' 2 7 j / 4 - ' 1 ' 2 7 j / 4 6 ' ' 7 7 7 @ 7 / - & % ? , 4 & / - , / & / - , / & / - , - & / - , 4 & / - , 4 & / - , / & / - , / & / - , 4 & / - , / & / - , / & / - , - & / - 7 7 4 ' 7 7 @ 7 - , . & % ? 7 7 / 7 7 4 7+1 pwm mode *
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pwm output control the pwm outputs are pin-shared with the i/o pins pa4, pd0 and pd3 respectively depending upon the selected device. to operate as a pwm output and not as an i/o pin, the correct bits must be set in the ctrl0 register. a zero value must also be written to the corresponding i/o port control bit to ensure that the corresponding pwm output pin is setup as an output. after these two initial steps have been carried out, and of course after the required pwm value has been written into the pwmn register, writing a high value to the corresponding i/o output data bit will enable the pwm data to appear on the pin. writing a zero value will disable the pwm output function and force the output low. in this way, the port data output registers can be used as an on/off control for the pwm function. note that if the ctrl0 register has selected the pwm function, but a high value has been written to its corresponding i/o port control bit to configure the pin as an input, then the pin can still function as a normal input line, with pull-high resistor options. pwm programming example the following sample program shows how the pwm0 output is setup and controlled. mov a,64h ; setup pwm value of decimal 100 mov pwm0,a set ctrl0.5 ; select the 7+1 pwm mode set ctrl0.3 ; select pin pa7 to have a pwm function clr pac.7 ; setup pin pa7 as an output set pa.7 ; enable the pwm output :: clr pa.7 ; disable the pwm output_ pin ; pa7 forced low rev. 1.00 66 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa
analog to digital converter the need to interface to real world analog signals is a common requirement for many electronic systems. however, to properly process these signals by a microcontroller, they must first be converted into digital signals by a/d converters. by integrating the a/d conversion electronic circuitry into the microcontroller, the need for external components is reduced significantly with the corresponding follow-on benefits of lower costs and reduced component space requirements. a/d overview the devices contain a multi-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and converts these signals directly into a 12-bit digital value. part no. input channels conversion bits input pins HT46R064G 2 12 pc4~pc5 ht46r065g 4 12 pc2~pc5 ht46r0662g 8 12 pc2~pc5 pd4~pd7 the accompanying block diagram shows the overall internal structure of the a/d converter, together with its associated registers. HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 67 march 3, 2011 $ 7 $ ) $ ) ! $ ) b $ & ) 7 ) ' 4 c ' - $ 4 c $ -
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a/d converter data registers adrl, adrh the device, which has an internal 12-bit a/d converter, requires two data registers, a high byte register, known as adrh, and a low byte register, known as adrl. after the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. only the high byte register, adrh, utilises its full 8-bit contents. the low byte register utilises only 4 bit of its 8-bit contents as it contains only the lowest bits of the 12-bit converted value. in the following table, d0~d11 is the a/d conversion data result bits. register bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 adrl d3 d2 d1 d0 adrh d11 d10 d9 d8 d7 d6 d5 d4 a/d data registers adrh, adrl register adrh adrl bit7654321076543210 name d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 r/wrrrrrrrrrrrr porxxxxxxxxxxxx x unknown unimplemented, read as 0 d11~d0 : adc conversion data a/d converter control registers adcr, acsr, ancsr to control the function and operation of the a/d converter, these control registers known as adcr, acsr and ancsr are provided. these 8-bit registers define functions such as the selection of which analog channel is connected to the internal a/d converter, which pins are used as analog inputs and which are used as normal i/os, the a/d clock source as well as controlling the start function and monitoring the a/d converter end of conversion status. the acs2~acs0 bits in the adcr register define the channel number. as the device contains only one actual analog to digital converter circuit, each of the individual 8 analog inputs must be routed to the converter. it is the function of the acs2~acs0 bits in the adcr register to determine which analog channel is actually connected to the internal a/d converter. the pcr7~pcr0 bits contained in the pcr or ancsr register which determine which pins on pc2~pc5 and pd4~pd7 are used as analog inputs for the a/d converter and which pins are to be used as normal i/o pins. if the pcrn bit has a value of 1, then the corresponding pin, namely one of the an0~an7 analog inputs, will be set as analog inputs. note that if the pcrn bit is set to zero, then the corresponding pin on pc2~pc5 and pd4~pd7 will be setup as a normal i/o pin for the ht46r0662g device. however, for the HT46R064G and ht46r065g devices, if the pcrn bits are all set to zero, the analog input channels will be all disabled and the a/d converter circuitry will be powered off. rev. 1.00 68 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa
adrh, adrl register adrh adrl bit7654321076543210 name d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 r/wrrrrrrrrrrrr porxxxxxxxxxxxx x unknown unimplemented, read as 0 d11~d0 : adc conversion data adcr register HT46R064G b i t76543210 name start eocb acs0 r/w r/w r r/w por 0 1 0 adcr register ht46r065g b i t76543210 name start eocb acs1 acs0 r/w r/w r r/w r/w por 0 1 00 adcr register ht46r0662g b i t76543210 name start eocb acs2 acs1 acs0 r/w r/w r r/w r/w r/w por 0 1 000 unimplemented, read as 0 start : start the a/d conversion 01 0 : start the a/d conversion 0 1 : reset the a/d converter and set eocb to 1 eocb : end of a/d conversion flag 0: a/d conversion ended 1: a/d conversion in progress acsn~acs0 : a/d channel selection for HT46R064G acs0 = 0: an0 acs0 = 1: an1 for ht46r065g acs1~acs0 = 00: an0 acs1~acs0 = 01: an1 acs1~acs0 = 10: an2 acs1~acs0 = 11: an3 for ht46r0662g acs2~acs0 = 000: an0; acs2~acs0 = 001: an1 acs2~acs0 = 010: an2; acs2~acs0 = 011: an3 acs2~acs0 = 100: an4; acs2~acs0 = 101: an5 acs2~acs0 = 110: an6; acs2~acs0 = 111: an7 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 69 march 3, 2011
acsr register HT46R064G/ht46r065g b i t76543210 name adcs1 adcs0 r/w r/w r/w por 00 acsr register ht46r0662g b i t76543210 name test adonb vrefs adcs2 adcs1 adcs0 r/w r/w r/w r/w r/w r/w r/w por 1 1 0 000 unimplemented, read as 0 test : for test mode use only adonb : adc module power on/off control bit 0: adc module power on 1: adc module power off note: 1. it is recommended to set adonb=1 before entering the idle/sleep mode to save power. 2. adonb =1 will power down the a/d converter module. vrefs : a/d converter reference voltage selection 0: internal a/d converter power 1: vref pin adcsn~adcs0 : select adc converter clock source for HT46R064G/HT46R064G adcs1~adcs0 = 00: f sys /2 adcs1~adcs0 = 01: f sys /8 adcs1~adcs0 = 10: f sys /32 adcs1~adcs0 = 11: undefined, cannot be used for ht46r0662g adcs2~adcs0 = 000: f sys /2 adcs2~adcs0 = 001: f sys /8 adcs2~adcs0 = 010: f sys /32 adcs2~adcs0 = 011: undefined, can not be used adcs2~adcs0 = 100: f sys adcs2~adcs0 = 101: f sys /4 adcs2~adcs0 = 110: f sys /16 adcs2~adcs0 = 111: undefined, can not be used rev. 1.00 70 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa
pcr register HT46R064G bit76543210 name pcr1 pcr0 r/w r/w r/w por 00 pcr register ht46r065g bit76543210 name pcr3 pcr2 pcr1 pcr0 r/w r/w r/w r/w r/w por 0000 unimplemented, read as 0 pcrn : define the analog input configuration (a/d input or not) 0: i/o or other pin-shared function 1: a/d input (ann input) note: if all the pcrn bits are zero, all the a/d analog input channels will be disabled and the a/d converter circuitry will be powered off. ancsr register ht46r0662g bit76543210 name pcr7 pcr6 pcr5 pcr4 pcr3 pcr2 pcr1 pcr0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 pcrn : define the analog input configuration (a/d input or not) 0: i/o or other pin-shared function 1: a/d input (ann input) a/d operation the start bit in the register is used to start and reset the a/d converter. when the microcontroller sets this bit from low to high and then low again, an analog to digital conversion cycle will be initi - ated. when the start bit is brought from low to high but not low again, the eocb bit in the adcr register will be set to 1 and the analog to digital converter will be reset. it is the start bit that is used to control the overall start operation of the internal analog to digital converter. the eocb bit in the adcr register is used to indicate when the analog to digital conversion process is complete. this bit will be automatically set to 0 by the microcontroller after a conversion cycle has ended. in addition, the corresponding a/d interrupt request flag will be set in the interrupt control register, and if the a/d interrupt is enabled, an appropriate internal interrupt signal will be gener - ated. this a/d internal interrupt signal will direct the program flow to the associated a/d internal in - terrupt address for processing. if the a/d internal interrupt is disabled, the microcontroller can be used to poll the eocb bit in the adcr register to check whether it has been cleared as an alternative method of detecting the end of an a/d conversion cycle. the clock source for the a/d converter, which originates from the system clock f sys , is first divided by a division ratio, the value of which is determined by the adcs2, adcs1 and adcs0 bits in the acsr register. HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 71 march 3, 2011
controlling the power on/off function of the a/d converter circuitry is implemented using the value of the adonb bit for the ht46r0662g device while it is implemented by setting all the pcrn bits to zero to power off the a/d converter circuitry for the HT46R064G and ht46r065g devices. although the a/d clock source is determined by the system clock f sys , and by bits adcs2, adcs1 and adcs0, there are some limitations on the a/d clock source speed range that can be selected. as the recommended range of permissible a/d clock period, t ad , is from 0.5 sto10 s, care must be taken for the selected system clock speeds. for example, if the system clock operates at a frequency of 2mhz or 4mhz, the adcs2, adcs1 and adcs0 bits should not be set to 010 or 100 respec - tively. doing so will give a/d clock periods that are greater than the maximum a/d clock period or less than the minimum a/d clock period which may result in inaccurate a/d conversion values. re - fer to the following table for examples, where values marked with an asterisk * show where, depend - ing upon the system clock speed, special care must be taken, as the values may be out of the specified a/d clock period range. f sys a/d clock period (t ad ) adcs2, adcs1, adcs0=000 (f sys /2) adcs2, adcs1, adcs0=001 (f sys /8) adcs2, adcs1, adcs0=010 (f sys /32) adcs2, adcs1, adcs0=100 (f sys) adcs2, adcs1, adcs0=101 (f sys /4) adcs2, adcs1, adcs0=110 (f sys /16) adcs2, adcs1, adcs0=011, 111 1mhz 2s8 s32 s* 1s4 s16 s* undefined 2mhz 1s4 s16 s 500ns 2s8 s undefined 4mhz 500ns 2s8 s 250ns* 1s4 s undefined 8mhz 250ns* 1s4 s 125ns* 500ns 2s undefined 12mhz 167ns* 667ns 2.67s 83ns* 333ns* 1s undefined a/d clock period examples a/d input pins all of the a/d analog input pins are pin-shared with the i/o pins on port c or port d respectively. bits pcr7~pcr0 in the pcr or ancsr register, determine whether the input pins are setup as normal input/output pins or whether they are setup as analog inputs. in this way, pins can be changed under program control to change their function from normal i/o operation to analog inputs and vice versa. pull-high resistors, which are setup through register programming, apply to the input pins only when they are used as normal i/o pins, if setup as a/d inputs the pull-high resistors will be automatically disconnected. note that it is not necessary to first setup the a/d pin as an input in the pcc or pdc port control registers to enable the a/d input as when the pcr7~pcr0 bits enable an a/d input, the status of the port control registers will be overridden. rev. 1.00 72 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa
summary of a/d conversion steps the following summarises the individual steps that should be executed in order to implement an a/d conversion process. step 1 select the required a/d conversion clock by correctly programming bits adcs2, adcs1 and adcs0 in the register. step 2 select which pins are to be used as a/d inputs and configure them as a/d input pins by correctly programming the pcr7~pcr0 bits in the ancsr or pcr register. step 3 enable the a/d converter by clearing the adonb bit in the acsr register zero. step 4 select which channel is to be connected to the internal a/d converter by correctly programming the acs2~acs0 bits which are also contained in the register. step 5 if the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the a/d converter interrupt function is active. the master interrupt control bit, emi, the intc0 interrupt control register must be set to 1, the a/d converter interrupt bit, ade, in the intc1 register must also be set to 1. step 6 the analog to digital conversion process can now be initialised by setting the start bit in the adcr register from 0 to 1 and then to 0 again. note that this bit should have been originally set to 0. step 7 to check when the analog to digital conversion process is complete, the eocb bit in the adcr register can be polled. the conversion process is complete when this bit goes low. when this occurs, the a/d data registers adrl and adrh can be read to obtain the conversion value. as an alternative method if the interrupts are enabled and the stack is not full, the program can wait for an a/d interrupt to occur. note: when checking for the end of the conversion process, if the method of polling the eocb bit in the adcr register is used, the interrupt enable step above can be omitted. the accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. the setting up and operation of the a/d converter function is fully under the control of the applica - tion program as there are no configuration options associated with the a/d converter. after an a/d conversion process has been initiated by the application program, the microcontroller internal hard - ware will begin to carry out the conversion, during which time the program can continue with other functions. the time taken for the a/d conversion is 16 t ad clock cycles where t ad is equal to the a/d clock period. HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 73 march 3, 2011
rev. 1.00 74 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa $ ) $ & ) 7 + 7 $ ) $ & ) 7 + 7 $ ) $ & ) 7 + 7 4 4 4 4 ( 7 7 4 4 ( 4 4 ( 7 7 4 ( / / / / ( 7 7 / / ( / 4 ( 7 7 / (
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programming considerations when programming the devices, special attention must be given to the pcrn bits in the pcr register for the HT46R064G and ht46r065g devices. if these bits are all cleared to zero, no external pins will be selected for use as a/d input pins allowing the pins to be used as normal i/o pins or other pin-shared functional pins. when this happens, the internal a/d circuitry will be power down. for the ht46r0662g device, setting the adonb bit high has the ability to power down the internal a/d circuitry, which may be an important consideration in power sensitive applications. a/d transfer function as the device contain a 12-bit a/d converter, its full-scale converted digitised value is equal to fffh. since the full-scale analog input value is equal to the vdd voltage, this gives a single bit analog input value of v dd /4096. the diagram show the ideal transfer function between the analog input value and the digitised output value for the a/d converter. note that to reduce the quantisation error, a 0.5 lsb offset is added to the a/d converter input. except for the digitised zero value, the subsequent digitised values will change at a point 0.5 lsb below where they would change without the offset, and the last full scale digitised value will change at a point 1.5 lsb below the v dd level. HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 75 march 3, 2011 * * b ; 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 < $ & ) 7 + * * * b * * ) b 4 6 b 4 - b 4 / b 4 : , 7 ! ( 4 / - 6 5 4 8 6 5 4 8 5 5 4 8 , 5 4 8 . $ 7 7 # / : , 7 ! ( # ) ) 7 7 # * 5 4 8 . ideal a/d transfer function
a/d programming example the following two programming examples illustrate how to setup and implement an a/d conversion for the ht46r0662g device. in the first example, the method of polling the eocb bit in the adcr register is used to detect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. example: using an eocb polling method to detect the end of conversion clr ade ; disable adc interrupt mov a,00000001b mov acsr,a ; select f sys /8 as a/d clock and adonb=0 mov a,00101011b ; setup ancsr to configure the ports as a/d inputs mov ancsr,a ; mov a,00000000b ; setup adcr to select an0 to be connected to the a/d converter mov adcr,a ; : : start_conversion: clr start set start ; reset a/d clr start ; start a/d polling_: sz eocb ; poll the adcr register eocb bit to detect end of a/d conversion jmp polling_eoc ; continue polling mov a,adrl ; read low byte conversion result value mov adrl_buffer,a ; save result to user defined register mov a,adrh ; read high byte conversion result value mov adrh_buffer,a ; save result to user defined register : jmp start_conversion ; start next a/d conversion note: to power off adc module, it is necessary to set adonb as 1 . example: using the interrupt method to detect the end of conversion clr ade ; disable adc interrupt mov a,00000001b mov acsr,a ; select f sys /8 as a/d clock and adonb=0 mov a,00101011b ; setup ancsr to configure the ports as a/d inputs mov ancsr,a ; mov a,00000000b ; setup adcr to select an0 to be connected to the a/d converter mov adcr,a ; : : start_conversion: clr start set start ; reset a/d clr start ; start a/d clr adf ; clear adc interrupt request flag set ade ; enable adc interrupt set emi ; enable global interrupt : : : ; adc interrupt service routine adc_: mov acc_stack,a ; save acc to user defined memory mov a,status mov status_stack,a ; save status to user defined memory : : mov a,adrl ; read low byte conversion result value mov adrl_buffer,a ; save result to user defined register mov a,adrh ; read high byte conversion result value mov adrh_buffer,a ; save result to user defined register : : exit_isr: mov a,status_stack mov status,a ; restore status from user defined memory mov a,acc_stack ; restore acc from user defined memory clr adf ; clear adc interrupt flag note: to power off the adc module, it is necessary to set adonb bit to high. rev. 1.00 76 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa
operational amplifiers there are two fully integrated operational amplifiers in these devices, opa0 and opa1. these opas can be used for user specified analog signal processing. the opas can be disabled or enabled entirely under software control using internal registers. with specific control registers, some opa related applications can be easily implemented, such as unity gain buffer, non-inverting amplifier, inverting amplifier and various kinds of filters, etc. comparator & operational amplifier registers the internal operational amplifiers are fully under the control of internal registers, copa0c, copa1c, copa2c, copa3c, opa0oc and opa1oc. these registers control the enable/disable function, input path selection, gain control, polarity and calibration function. operational amplifier operation the advantages of multiple switches and input path options, various reference voltage selection, up to 8 kinds of internal software gain control, output with interrupt function, offset reference voltage calibration function and power down control for low power consumption enhance the flexibility of these two opas to suit a wide range of application possibilities. note that the ea0i, ea1i interrupt control bits should be set to 0 before entering halt mode for power saving. the following block diagram illustrates the main functional blocks of the opas and comparator in this device. HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 77 march 3, 2011 c cn cp 0.7vdd 0.5vdd 0.1vdd mux mux a1x a1 a1n a1p 0.7vdd 0.5vdd 0.1vdd mux mux a0 a0n a0p 0.7vdd 0.5vdd 0.1vdd mux 10k 500k s11 a0x s13 s12 s24 s21 s22 s23 r1 r2 a0x a1x ma0p ma1n ma1p mcn mcp pol cx (cout) cx mux tc0 pin to timer 0 external clock input tmr0s a1ps[2:0] a1ns[1:0] cns[1:0] cps[2:0] a0ps[2:0] debounce to opa0 interrupt to opa1 interrupt edge control to interrupt cints[1:0] =00: rasing edge =01: falling edge =10: both edge ea0i ea1i
copa0c register b i t76543210 name a0ps2 a0ps1 a0ps0 cps2 cps1 cps0 cns1 cns0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7~5 a0ps2~a0ps0 : opa0 non-inverting input signal selection bits 000: a0p pin 001: 0.7v dd 010: 0.5v dd 011: 0.1v dd 100: v ss 101~111: undefined bit 4~2 cps2~cps0 : comparator non-inverting input signal selection bits 000: cp pin 001: 0.7v dd 010: 0.5v dd 011: 0.1v dd 100: v ss 101~111: undefined bit 1~0 cns1~cns0 : comparator inverting input signal selection bits 00: cn pin 01: a1x 10: v ss 11: undefined copa1c register b i t76543210 name a1g2 a1g1 a1g0 a1ps2 a1ps1 a1ps0 a1ns1 a1ns0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7~5 a1g2~a1g0 : opa1 gain control bits 000: 6.25 001: 12.50 010: 18.75 011: 25.00 100: 31.25 101: 37.50 110: 43.75 111: 50.00 bit 4~2 a1ps2~a1ps0 : opa1 non-inverting input signal selection bits 000: a1p pin 001: 0.7v dd 010: 0.5v dd 011: 0.1v dd 100: v ss 101: a0x, the opa0 internal output 110~111: undefined bit 1~0 a1ns1~a1ns0 : opa1 inverting input signal selection bits 00: a1n pin 01: a0x, the opa0 internal output 10: v ss 11: undefined rev. 1.00 78 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa
copa2c register b i t76543210 name s24 s23 s22 s21 s13 s12 s11 cxc r/w r/w r/w r/w r/w r/w r/w r/w r/w p o r00000000 bit 7 s24 : switch s24 on/off control bit 0: off 1: on bit 6 s23 : switch s23 on/off control bit 0: off 1: on bit 5 s22 : switch s22 on/off control bit 0: off 1: on bit 4 s21 : switch s21 on/off control bit 0: off 1: on bit 3 s13 : switch s13 on/off control bit 0: off 1: on bit 2 s12 : switch s12 on/off control bit 0: off 1: on bit 1 s11 : switch s11 on/off control bit 0: off 1: on bit 0 cxc : comparator output pin cx enable control bit 0: i/o pin or other pin-shared functional pin 1: cx output pin (i/o pull-high disabled) copa3c register b i t76543210 name a1xc a1pc a1nc a0xc a0pc a0nc cpc cnc r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7 a1xc : opa1 output pin a1x enable control bit 0: i/o pin or other pin-shared functional pin 1: a1x output pin (i/o pull-high disabled) bit 6 a1pc : opa1 non-inverting input pin a1p enable control bit 0: i/o pin or other pin-shared functional pin 1: a1p input pin (i/o pull-high disabled) bit 5 a1nc : opa1 inverting input pin a1n enable control bit 0: i/o pin or other pin-shared functional pin 1: a1n input pin (i/o pull-high disabled) bit 4 a0xc : opa0 output pin a0x enable control bit 0: i/o pin or other pin-shared functional pin 1: a0x output pin (i/o pull-high disabled) bit 3 a0pc : opa0 non-inverting input pin a0p enable control bit 0: i/o pin or other pin-shared functional pin 1: a0p input pin (i/o pull-high disabled) bit 2 a0nc : opa0 inverting input pin a0n enable control bit 0: i/o pin or other pin-shared functional pin 1: a0n input pin (i/o pull-high disabled) HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 79 march 3, 2011
bit 1 cpc : comparator non-inverting input pin cp enable control bit 0: i/o pin or other pin-shared functional pin 1: cp input pin (i/o pull-high disabled) bit 0 cnc : comparator inverting input pin cn enable control bit 0: i/o pin or other pin-shared functional pin 1: cn input pin (i/o pull-high disabled) opa0oc register b i t76543210 name a0en a0op a0ofm a0rs a0of3 a0of2 a0of1 a0of0 r/w r/w r r/w r/w r/w r/w r/w r/w por00000000 bit 7 a0en : operational amplifier 0 enable control bit 0: disable 1: enable bit 6 a0op : operational amplifier 0 output; positive logic. this bit is read only bit. bit 5 a0ofm : operational amplifier 0 normal mode or input offset voltage cancellation mode selection bit 0: operational amplifier 0 normal mode 1: input offset voltage cancellation mode bit 4 a0rs : operational amplifier 0 input offset voltage cancellation reference input selection bit 0: operational amplifier a0n as the reference input 1: operational amplifier a0p as the reference input bit 3~0 a0of3~a0of0 : operational amplifier 0 input offset voltage cancellation control bits opa1oc register b i t76543210 name a1en a1op a1ofm a1rs a1of3 a1of2 a1of1 a1of0 r/w r/w r r/w r/w r/w r/w r/w r/w por00000000 bit 7 a1en : operational amplifier 1 enable control bit 0: disable 1: enable bit 6 a1op : operational amplifier 1 output; positive logic. this bit is read only bit. bit 5 a1ofm : operational amplifier 1 normal mode or input offset voltage cancellation mode selection bit 0: operational amplifier 1 normal mode 1: input offset voltage cancellation mode bit 4 a1rs : operational amplifier 1 input offset voltage cancellation reference input selection bit 0: operational amplifier a1n as the reference input 1: operational amplifier a1p as the reference input bit 3~0 a1of3~a1of0 : operational amplifier 1 input offset voltage cancellation control bits rev. 1.00 80 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa
operational amplifier application example the opas can be connected to work with each other or standalone as shown in the block diagram. with the software controlled switch and mux, the opas can be connected to form various opa related applications, such as, unity gain buffer, non-inverting amplifier, inverting amplifier, integrators, differential amplifier, low-pass filter, high-pass filter and band-pass filter,etc. the following diagrams show the interconnection and settings between the opas to implement these applications. the following examples are however only for reference. unity gain buffer example implementation connection unity gain buffer switch setup bit 76543210 opa2c s24 s23 s22 s21 s13 s12 s11 cxc setup value xxxx110x x don t care bit 76543210 opa0c a0ps2 a0ps1 a0ps0 cps2 cps1 cps0 cns1 cns0 setup value 00000000 switch control bits options: s11: off s12: on s13: on a0ps[2:0]: 000 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 81 march 3, 2011
7 ' $ 4 7 7 7 $ 4 $ 4 ' 9 4 : 0 # ) ) 4 : , # ) ) 4 : / # ) ) $ 4 ' - c $ 4 ' 4 $ 4 3 $ 4 ' $ 4 9 / - 7 3 / / 7 * * / 6 7 3 # 3 #
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non-inverting amplifier example implementation connection non-inverting amplifier switch setup bit 76543210 opa2c s24 s23 s22 s21 s13 s12 s11 cxc setup value xxxx101x x don t care bit 76543210 opa0c a0ps2 a0ps1 a0ps0 cps2 cps1 cps0 cns1 cns0 setup value 00000000 switch control bits options: s11: on s12: off s13: on a0ps[2:0]: 000 rev. 1.00 82 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa # 3 #
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inverting amplifier example implementation connection inverting amplifier switch setup bit 76543210 opa2c s24 s23 s22 s21 s13 s12 s11 cxc setup value xxxx101x x don t care bit 76543210 opa0c a0ps2 a0ps1 a0ps0 cps2 cps1 cps0 cns1 cns0 setup value 10000000 switch control bits options: s11: on s12: off s13: on a0ps[2:0]: 100 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 83 march 3, 2011 # 3 #
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two-stage non-inverting amplifier example implementation connection two-stage non-inverting amplifier switch setup bit 76543210 opa2c s24 s23 s22 s21 s13 s12 s11 cxc setup value 1100101x x don t care bit 76543210 opa0c a0ps2 a0ps1 a0ps0 cps2 cps1 cps0 cns1 cns0 setup value 00000000 bit 76543210 opa1c a1g2 a1g1 a1g0 a1ps2 a1ps1 a1ps0 a1ns1 a1ns0 setup value 00010110 switch control bits options: s11: on s12: off s13: on s21: off s22: off s23: on s24: on a0ps[2:0]: 000 a1ps[2:0]: 101 a1ns[1:0]: 10 a1g[2:0]: user define opa1 gain control rev. 1.00 84 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa a1 0.7vdd 0.5vdd 0.1vdd mux mux a0 a0n a0p 0.7vdd 0.5vdd 0.1vdd mux r1 10k r2 500k a0x a0x a1x ma0p ma1n ma1p a1ps[2:0] a1ns[1:0] a0ps[2:0] ea0i ea1i a1x vin to opa1 interrupt or comparator input to opa0 interrupt or comparator input a1n a1p s12 off s11 on s13 on s22 off s23 on s24 on r3 r4 s21 off #
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two-stage inverting amplifier example implementation connection two-stage inverting amplifier switch setup bit 76543210 opa2c s24 s23 s22 s21 s13 s12 s11 cxc setup value 1100101x x don t care bit 76543210 opa0c a0ps2 a0ps1 a0ps0 cps2 cps1 cps0 cns1 cns0 setup value 10000000 bit 76543210 opa1c a1g2 a1g1 a1g0 a1ps2 a1ps1 a1ps0 a1ns1 a1ns0 setup value 00010001 switch control bits options: s11: on s12: off s13: on s21: off s22: off s23: on s24: on a0ps[2:0]: 100 a1ps[2:0]: 100 a1ns[1:0]: 01 a1g[2:0]: user define opa1 gain control HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 85 march 3, 2011 a1 0.7vdd 0.5vdd 0.1vdd mux mux a0 a0n a0p 0.7vdd 0.5vdd 0.1vdd mux r1 10k r2 500k a0x a0x a1x ma0p ma1n ma1p a1ps[2:0] a1ns[1:0] a0ps[2:0] ea0i ea1i a1x vin a1n a1p to opa0 interrupt or comparator input to opa1 interrupt or comparator input s12 off s11 on s13 on s22 off s23 on s24 on s21 off r4 r3 #
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integrator example implementation connection integrator switch setup bit 76543210 opa2c s24 s23 s22 s21 s13 s12 s11 cxc setup value 1001 xxxx x don t care bit 76543210 opa0c a0ps2 a0ps1 a0ps0 cps2 cps1 cps0 cns1 cns0 setup value 00010000 switch control bits options: s21: on s22: off s23: off s24: on a1ps[2:0]: 100 a1ns[1:0]: 00 a1g[2:0]: user define opa1 gain control rev. 1.00 86 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa a1 a1n a1p 0.7vdd 0.5vdd 0.1vdd mux mux 10k 500k ma1n ma1p a1ps[2:0] a1ns[1:0] a0x a1x a1x ea1i vin to opa1 interrupt or comparator input s22 off s23 off s24 on r1 c s21 on #
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low pass filter example implementation connection low pass filter switch setup bit 76543210 opa2c s24 s23 s22 s21 s13 s12 s11 cxc setup value xxxx101x x don t care bit 76543210 opa0c a0ps2 a0ps1 a0ps0 cps2 cps1 cps0 cns1 cns0 setup value 10000000 switch control bits options: s11: on s12: off s13: on a0ps[2:0]: 100 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 87 march 3, 2011 a0 a0n 0.7vdd 0.5vdd 0.1vdd mux a0x ma0p a0ps[2:0] vin to opa0 interrupt or comparator input s12 off s11 on s13 on r1 r2 c #
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operational amplifier offset cancellation function each of the internal opas allows for a common mode adjustment method of its input offset voltage. a0rs a0ofm s1a s2a s3a 0 0 on on off 0 1 off on on 1 0 on on off 1 1 on off on a1rs a1ofm s1b s2b s3b 0 0 on on off 0 1 off on on 1 0 on on off 1 1 on off on the calibration steps are as following: 1. set a0ofm=1 to setup the offset cancellation mode, here s3a is closed. 2. set a0rs to select which input pin is to be used as the reference voltage - s1 or s2 is closed 3. adjust a0of0~a0of3 until the output status changes 4. set a0of m=0to restore the normal opa mode 5. repeat the same procedure from steps 1 to 4 for opa1. rev. 1.00 88 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa $ 4 ' $ 4 3 $ 4 9 / $ - $ 6 $ $ 4 * 4 c $ 4 * 6 $ 4 3 $ 4 ' $ / ' $ / 3 $ / 9 / ( - ( 6 ( $ / * 4 c $ / * 6 $ / 3 $ / ' / : , >
comparator these devices contain a fully integrated comparator whose operation is controlled by the comparator control registers, known as the cmp0c, cmp1c, copa0c, copa2c and copa3c registers. the cen bit within cmp0c register is used as the enable or disable bit for the comparator function. the advantages of multiple input resources, multiple reference voltage options, output polarity control, output to timer counter, multiple output interrupt triggers, comparator output wakeup mcu function, comparator output with de-bounce options, comparator operating current selection and power down control for low power consumption enhance the flexibility of this comparator to suit a wide range of application possibilities. comparator functions the comparator can work with opas or standalone as shown in the main functional blocks of the opas and comparator in this device. this comparator provides three operating current options, which are 200 a, 5 a and 1 a. the purpose of this design is to provide the suitable comparator power consumption for different operating modes of the device. the higher the operating current, the shorter the comparator response time, therefore, the designer can select the higher operating current for the device working at normal mode and a lower one for the device entering power down mode. by this way, this comparator can operate under very low power consumption and perform as a wakeup resource when the device enters power down mode. in addition, this device provides different comparator output de-bounce time options for different input signal. if the input signal is noise sensitive, then the better choice will be the longer de-bounce time. the designer could select the suitable de-bounce time according to the input signal. cmp0c register bit76543210 name cen cpol cout dbc1 dbc0 cpcs1 cpcs0 r/w r/w r/w r r/w r/w r/w r/w por00000000 bit 7 unimplemented, read as 0 bit 6 cen : comparator on/off bit 0: off 1: on note that the designer should enable the comparator first before enabling the comparator interrupt, in order to prevent an unexpected interrupt. bit 5 cpol : comparator output polarity control bit 0: not inverted 1: inverted bit 4 cout : comparator output bit. cpol=0: if the cp pin input voltage is less than cn pin, then the cout is 0. if the cp pin input voltage is greater than cn pin, then the cout is 1. cpol=1: if the cp pin input voltage is less than cn pin, then the cout is 1. if the cp pin input voltage is greater than cn pin, then the cout is 0. bit 3~2 dbc1, dbc0 : de-bounce time selection, up to application signal 00: no de-bounce 01: de-bounce time= 1 system clock 10: de-bounce time= 4 system clock 11: de-bounce time= 16 system clock bit 1~0 cpcs1, cpcs0] : comparator operating current selection for low power consumption 00: 200 a 01: 5 a 10: 1 a 11: not implemented HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 89 march 3, 2011
cmp1c register bit76543210 name a0vrc a1vrc cpvrc tmr0s cints1 cints0 r/w r/w r/w r/w r/w r/w r/w por00000000 bit7 a0vrc : opa0 non-inverting input connection control bit 0: connected to internal reference voltage only 1: connected to both internal reference voltage and external i/o (a0p) pin bit6 a1vrc : opa1 non-inverting input connection control bit 0: connected to internal reference voltage only 1: connected to both internal reference voltage and external i/o (a1p) pin bit5 cpvrc : comparator non-inverting input connection control bit 0: connected to internal reference voltage only 1: connected to both internal reference voltage and external i/o (cp) pin note that the above setting of these three bits, which are a0vrc, a1vrc and cpvrc, is valid when the non inverting input pins are selected to be connected to the internal reference voltage by a0ps[2:0],a1ps[2:0] and cps[2:0] control bits respectively. bit 4, 2 unimplemented, read as 0 bit 3 tmr0s : signal input path selection for timer 0 event counter 0: from tc0 pin 1: from comparator output bit 1~0 cints1, cints0 : comparator interrupt trigger type selection 00: falling edge 01: rising edge 10: both edge 11: reserved rev. 1.00 90 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa
interrupts interrupts are an important part of any microcontroller system. when an external event or an internal function such as a timer/event counter or time base requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. the devices contain a single external interrupt and multiple internal interrupts. the external interrupt is controlled by the action of the external interrupt pin, while the internal interrupts are controlled by the various functions such as timer/event counters and time base overflow, etc. interrupt register overall interrupt control, which means interrupt enabling and request flag setting, is controlled by using the registers, intc0 and intc1. by controlling the appropriate enable bits in the registers each individual interrupt can be enabled or disabled. also when an interrupt occurs, the corresponding request flag will be set by the microcontroller. the global enable control bit if cleared to zero will disable all interrupts. intc0 register HT46R064G b i t76543210 name t0f intf t0e inte emi r/w r/w r/w r/w r/w r/w por 00 000 bit 7~6 unimplemented, read as 0 bit 5 t0f : timer/event counter 0 interrupt request flag 0: inactive 1: active bit 4 intf : external interrupt request flag 0: inactive 1: active bit 3 unimplemented, read as 0 bit 2 t0e : timer/event counter 0 interrupt enable 0: disable 1: enable bit 1 inte : external interrupt enable 0: disable 1: enable bit 0 emi : master interrupt global enable 0: disable 1: enable HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 91 march 3, 2011
intc0 register ht46r065g/ht46r0662g b i t76543210 name t1f t0f intf t1e t0e inte emi r/w r/w r/w r/w r/w r/w r/w r/w por 0000000 bit 7 unimplemented, read as 0 bit 6 t1f : timer/event counter 1 interrupt request flag 0: inactive 1: active bit 5 t0f : timer/event counter 0 interrupt request flag 0: inactive 1: active bit 4 intf : external interrupt request flag 0: inactive 1: active bit 3 t1e : timer/event counter 1 interrupt enable 0: disable 1: enable bit 2 t0e : timer/event counter 0 interrupt enable 0: disable 1: enable bit 1 inte : external interrupt enable 0: disable 1: enable bit 0 emi : master interrupt global enable 0: disable 1: enable intc1 register all devices b i t76543210 name mff tbf adf mfe tbe ade r/w r/w r/w r/w r/w r/w r/w por 000 000 bit 7 unimplemented, read as 0 bit 6 mff : multi-function interrupt request flag 0: inactive 1: active bit 5 tbf : time base event interrupt request flag 0: inactive 1: active bit 4 adf : a/d conversion interrupt request flag 0: inactive 1: active bit 3 unimplemented, read as 0 bit 2 mfe : multi-function interrupt enable 0: disable 1: enable bit 1 tbe : time base event interrupt enable 0: disable 1: enable bit 0 ade : a/d conversion interrupt enable 0: disable 1: enable rev. 1.00 92 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa
mfic register all devices b i t76543210 name a1f a0f cf ea1i ea0i eci r/w r/w r/w r/w r/w r/w r/w por 000 000 bit 7 unimplemented, read as 0 bit 6 a1f : opa1 interrupt request flag 0: inactive 1: active bit 5 a0f : opa0 interrupt request flag 0: inactive 1: active bit 4 cf : comparator interrupt request flag 0: inactive 1: active bit 3 unimplemented, read as 0 bit 2 ea1i : opa1 interrupt enable 0: disable 1: enable bit 1 ea0i : opa0 interrupt enable 0: disable 1: enable bit 0 eci : comparator interrupt enable 0: disable 1: enable interrupt operation a timer/event counter overflow, a completion of a/d conversion, an active edge on the external interrupt pin, a comparator output transition, an opa output falling edge or a time base event will all generate an interrupt request by setting their corresponding request flag. when this happens, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. the microcontroller will then fetch its next instruction from this interrupt vector. the instruction at this vector will usually be a jmp statement which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated with a reti instruction, which retrieves the original program counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. the various interrupt enable bits, together with their associated request flags, are shown in the following diagram with their order of priority. once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the emi bit will be cleared automatically. this will prevent any further interrupt nesting from occurring. however, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded. if an interrupt requires immediate servicing while the program is already in another interrupt service routine, the emi bit should be set after entering the routine, to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. when an interrupt request is generated it takes 2 or 3 instruction cycle before the program jumps to the interrupt vector. if the device is in the sleep or idle mode and is woken up by an interrupt request then it will take 3 cycles before the program jumps to the interrupt vector. HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 93 march 3, 2011
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5 . 4 . . - d 7 : interrupt scheme wait for 2 ~ 3 instruction cycles main program isr entry enable bit set ? main program reti (it will set emi automatically) automatically disable interrupt clear emi & request flag interrupt request or interrupt flag set by instruction y n interrupt flow
interrupt priority interrupts, occurring in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding interrupts are enabled. in case of simultaneous requests, the following table shows the priority that is applied. these can be masked by resetting the emi bit. HT46R064G interrupt source priority vector external interrupt 1 04h timer/event counter 0 overflow 2 08h a/d conversion complete 3 10h time base overflow 4 14h multi-function interrupt (comparator, opa0, opa1) 5 18h ht46r065g/ht46r0662g interrupt source priority vector external interrupt 1 04h timer/event counter 0 overflow 2 08h timer/event counter 1 overflow 3 0ch a/d conversion complete 4 10h time base overflow 5 14h multi-function interrupt (comparator, opa0, opa1) 6 18h in cases where both external and internal interrupts are enabled and where an external and internal in- terrupt occurs simultaneously, the external interrupt will always have priority and will therefore be serviced first. suitable masking of the individual interrupts using the interrupt registers can prevent simultaneous occurrences. HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 95 march 3, 2011
external interrupt for an external interrupt to occur, the global interrupt enable bit, emi, and external interrupt enable bit, inte, must first be set. an actual external interrupt will take place when the external interrupt request flag, intf, is set, a situation that will occur when an edge transition appears on the external int line. the type of transition that will trigger an external interrupt, whether high to low, low to high or both is determined by the integ0 and integ1 bits, which are bits 6 and 7 respectively, in the ctrl1 control register. these two bits can also disable the external interrupt function. integ1 integ0 edge trigger type 0 0 external interrupt disable 0 1 rising edge trigger 1 0 falling edge trigger 1 1 both edge trigger the external interrupt pin is pin-shared with the i/o pin pa3 and can only be configured as an exter - nal interrupt pin if the corresponding external interrupt enable bit in the intc register has been set and the edge trigger type has been selected using the ctrl1 register. the pin must also be setup as an input by setting the corresponding pac.3 bit in the port control register. when the interrupt is en - abled, the stack is not full and an active transition appears on the external interrupt pin, a subroutine call to the external interrupt vector at location 04h, will take place. when the interrupt is serviced, the external interrupt request flag, intf, will be automatically reset and the emi bit will be automati - cally cleared to disable other interrupts. note that any pull-high resistor connections on this pin will remain valid even if the pin is used as an external interrupt input. timer/event counter interrupt for a timer/event counter interrupt to occur, the global interrupt enable bit, emi, and the corresponding timer interrupt enable bit, tne, must first be set. an actual timer/event counter interrupt will take place when the timer/event counter request flag, tnf, is set, a situation that will occur when the relevant timer/event counter overflows. when the interrupt is enabled, the stack is not full and a timer/event counter n overflow occurs, a subroutine call to the relevant timer interrupt vector, will take place. when the interrupt is serviced, the timer interrupt request flag, tnf, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. a/d converter interrupt for an a/d interrupt to occur, the global interrupt enable bit emi and the corresponding interrupt enable bit ade must be first set. an actual a/d interrupt will take place when the a/d converter request flag adf is set, a situation that will occur when an a/d conversion process has completed. when the interrupt is enabled, the stack is not full and an a/d conversion process finishes execution, a subroutine call to the relevant a/d interrupt vector, will take place. when the interrupt is serviced, the a/d interrupt request flag adf will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. as this interrupt vector location is shared with other interrupts, to be effective it must be selected via configuration option. time base interrupt for a time base interrupt to occur the global interrupt enable bit emi and the corresponding interrupt enable bit tbe, must first be set. an actual time base interrupt will take place when the time base request flag tbf is set, a situation that will occur when the time base overflows. when the interrupt is enabled, the stack is not full and a time base overflow occurs a subroutine call to time base vector will take place. when the interrupt is serviced, the time base interrupt flag. tbf will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. rev. 1.00 96 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa
multi-function interrupt for a multi-function interrupt to occur, the global interrupt enable bit, emi, and the corresponding multi-function interrupt enable bit, mfe, must first be set. an actual multi-function interrupt will take place when the multi-function interrupt request flag, mff, is set, a situation that will occur when opa0 or opa1 output has a falling edge, or a comparator output transition occurs. when the interrupt is enabled, the stack is not full and a multi-function interrupt request occurs, a subroutine call to the multi-function interrupt vector at location 18h, will take place. when the interrupt is serviced, the multi-function interrupt request flag, mff, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. after the multi-function took place, the programmer can check what the interrupt source was by interrogating the request flags, a0f, a1f or cf within the mfic register. programming considerations by disabling the interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by a software instruction. it is recommended that programs do not use the call subroutine instruction within the interrupt subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. if only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. all of these interrupts have the capability of waking up the processor when in the idle/sleep mode. only the program counter is pushed onto the stack. if the contents of the register or status register are altered by the interrupt service program, which may corrupt the desired control sequence, then the contents should be saved in advance. scom function for lcd the ht46r065g and ht46r0662g devices have the capability of driving external lcd panels. the common pins for lcd driving, scom0~scom3, are pin shared with certain pin on the pb0~pb3 port. the lcd signals (com and seg) are generated using the application program. lcd operation an external lcd panel can be driven using this device by configuring the pb0~pb3 pins as common pins and using other output ports lines as segment pins. the lcd driver function is controlled using the scomc register which in addition to controlling the overall on/off function also controls the bias voltage setup function. this enables the lcd com driver to generate the necessary v dd /2 voltage levels for lcd 1 / 2 bias operation. HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 97 march 3, 2011 # ) ) 4 c 6 3 3 # ) ) & - 7 7 lcd com bias
the scomen bit in the scomc register is the overall master control for the lcd driver, however this bit is used in conjunction with the comnen bits to select which port b and port c pins are used for lcd driving. note that the port control register does not need to first setup the pins as outputs to enable the lcd driver operation. scomen comnen pin function o/p level 0 x i/o 0or1 1 0 i/o 0or1 1 1 scomn v dd /2 output control lcd bias control the lcd com driver enables a range of selections to be provided to suit the requirement of the lcd panel which is being used. the bias resistor choice is implemented using the isel1 and isel0 bits in the scomc register. scomc register b i t76543210 name isel1 isel0 scomen com3en com2en com1en com0en r/w r/w r/w r/w r/w r/w r/w r/w r/w por 00000000 bit 7 reserved bit 1: unpredictable operation - bit must not be set high 0: correct level - bit must be reset to zero for correct operation bit 6,5 isel1, isel0 : scom operating current selection (v dd =5v) 00: 25 a 01: 50 a 10: 100 a 11: 200 a bit 4 scomen : scom module on/off control 0: disable 1: enable scomn can be enable by comnen if scomen=1 bit 3 com3en : pc6 or scom3 selection 0: gpio 1: scom3 bit 2 com2en : pc7 or scom2 selection 0: gpio 1: scom2 bit 1 com1en : pb7 or scom1 selection 0: gpio 1: scom1 bit 0 com0en : pb6 or scom0 selection 0: gpio 1: scom0 rev. 1.00 98 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa
configuration options configuration options refer to certain options within the mcu that are programmed into the otp program memory device during the programming process. during the development process, these options are selected using the ht-ide software development tools. as these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later by the application software. all options must be defined for proper system function, the details of which are shown in the table. no. options 1 watchdog timer: enable or disable 2 watchdog timer clock source: lxt, lirc or f sys /4 note: lxt oscillator must be selected by osc configuration option if wdt clock source is from lxt. 3 clrwdt instructions: 1 or 2 instructions 4 for HT46R064G/ht46r065g system oscillator configuration: hxt, hirc, erc, hirc+lxt for ht46r0662g system oscillator configuration: hxt, hirc, erc, hxt+lxt, hirc+lxt, erc+lxt 5 lvr function: enable or disable 6 lvr voltage: 2.1v, 3.15v or 4.2v 7 res or pa7 pin function 8 hirc oscillator frequency: 4mhz, 8mhz or 12mhz application circuits HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 99 march 3, 2011 ' $ . & / ' $ , & -
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instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5 s and branch or call instructions would be implemented within 1 s. although instructions which require one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instructions would be clr pcl or mov pcl, a . for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specific immediate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on program requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application where rotate data operations are used is to implement multiplication and division calculations. rev. 1.00 100 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa
branches and control transfer program branching takes the form of either jumps to specified locations using the jmp instruction or to a subroutine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made regarding the condition of a certain data memory or individual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the ability to provide single bit operations on data memory is an extremely flexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively. the feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is taken care of automatically when these bit operation instructions are used. table read operations data storage is normally implemented by using registers. however, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the data memory. to overcome this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the halt instruction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections. HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 101 march 3, 2011
instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. table conventions: x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from the acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry, result in data memory decimal adjust acc for addition with result in data memory 1 1 note 1 1 1 note 1 1 1 note 1 1 note 1 note z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] logical and data memory to acc logical or data memory to acc logical xor data memory to acc logical and acc to data memory logical or acc to data memory logical xor acc to data memory logical and immediate data to acc logical or immediate data to acc logical xor immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 note 1 note 1 note 1 1 1 1 note 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 note 1 1 note z z z z rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 note 1 1 note 1 1 note 1 1 note none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 note 1 none none none rev. 1.00 102 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa
mnemonic description cycles flag affected bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 note 1 note none none branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read table (current page) to tblh and data memory read table (last page) to tblh and data memory 2 note 2 note none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 note 1 note 1 1 1 1 note 1 1 none none none to, pdf to, pdf to, pdf none none to, pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt1 and clr wdt2 instructions the to and pdf flags may be affected by the execution status. the to and pdf flags are cleared after both clr wdt1 and clr wdt2 instructions are consecutively executed. otherwise the to and pdf flags remain unchanged. HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 103 march 3, 2011
instruction definition adc a,[m] add data memory to acc with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the accumulator. operation acc acc+[m]+c affected flag(s) ov, z, ac, c adcm a,[m] add acc to data memory with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the specified data memory. operation [m] acc + [m] + c affected flag(s) ov, z, ac, c add a,[m] add data memory to acc description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc + [m] affected flag(s) ov, z, ac, c add a,x add immediate data to acc description the contents of the accumulator and the specified immediate data are added. the result is stored in the accumulator. operation acc acc+x affected flag(s) ov, z, ac, c addm a,[m] add acc to data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the specified data memory. operation [m] acc + [m] affected flag(s) ov, z, ac, c and a,[m] logical and data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and [m] affected flag(s) z and a,x logical and immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and x affected flag(s) z andm a,[m] logical and acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical and operation. the result is stored in the data memory. operation [m] acc and [m] affected flag(s) z rev. 1.00 104 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa
call addr subroutine call description unconditionally calls a subroutine at the specified address. the program counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specified address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cy - cle instruction. operation stack program counter + 1 program counter addr affected flag(s) none clr [m] clear data memory description each bit of the specified data memory is cleared to 0. operation [m] 00h affected flag(s) none clr [m].i clear bit of data memory description bit i of the specified data memory is cleared to 0. operation [m].i 0 affected flag(s) none clr wdt clear watchdog timer description the to, pdf flags and the wdt are all cleared. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt1 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in con- junction with clr wdt2 and must be executed alternately with clr wdt2 to have ef- fect. repetitively executing this instruction without alternately executing clr wdt2 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt2 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in con - junction with clr wdt1 and must be executed alternately with clr wdt1 to have ef - fect. repetitively executing this instruction without alternately executing clr wdt1 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 105 march 3, 2011
cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. operation [m] [m] affected flag(s) z cpla [m] complement data memory with result in acc description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain un - changed. operation acc [m] affected flag(s) z daa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd ( binary coded decimal) value resulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac flag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c flag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by adding 00h, 06h, 60h or 66h depending on the accumulator and flag conditions. only the c flag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m] acc + 00h or [m] acc + 06h or [m] acc + 60h or [m] acc + 66h affected flag(s) c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] [m] 1 affected flag(s) z deca [m] decrement data memory with result in acc description data in the specified data memory is decremented by 1. the result is stored in the accu - mulator. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) z halt enter power down mode description this instruction stops the program execution and turns off the system clock. the con - tents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down flag pdf is set and the wdt time-out flag to is cleared. operation to 0 pdf 1 affected flag(s) to, pdf rev. 1.00 106 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa
inc [m] increment data memory description data in the specified data memory is incremented by 1. operation [m] [m]+1 affected flag(s) z inca [m] increment data memory with result in acc description data in the specified data memory is incremented by 1. the result is stored in the accu - mulator. the contents of the data memory remain unchanged. operation acc [m]+1 affected flag(s) z jmp addr jump unconditionally description the contents of the program counter are replaced with the specified address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. operation program counter addr affected flag(s) none mov a,[m] move data memory to acc description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) none mov a,x move immediate data to acc description the immediate data specified is loaded into the accumulator. operation acc x affected flag(s) none mov [m],a move acc to data memory description the contents of the accumulator are copied to the specified data memory. operation [m] acc affected flag(s) none nop no operation description no operation is performed. execution continues with the next instruction. operation no operation affected flag(s) none or a,[m] logical or data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical or operation. the result is stored in the accumulator. operation acc acc or [m] affected flag(s) z HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 107 march 3, 2011
or a,x logical or immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical or operation. the result is stored in the accumulator. operation acc acc or x affected flag(s) z orm a,[m] logical or acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical or operation. the result is stored in the data memory. operation [m] acc or [m] affected flag(s) z ret return from subroutine description the program counter is restored from the stack. program execution continues at the re - stored address. operation program counter stack affected flag(s) none ret a,x return from subroutine and load immediate data to acc description the program counter is restored from the stack and the accumulator loaded with the specified immediate data. program execution continues at the restored address. operation program counter stack acc x affected flag(s) none reti return from interrupt description the program counter is restored from the stack and the interrupts are re-enabled by set- ting the emi bit. emi is the master interrupt global enable bit. if an interrupt was pend- ing when the reti instruction is executed, the pending interrupt routine will be processed before returning to the main program. operation program counter stack emi 1 affected flag(s) none rl [m] rotate data memory left description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 affected flag(s) none rla [m] rotate data memory left with result in acc description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data mem - ory remain unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 [m].7 affected flag(s) none rev. 1.00 108 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa
rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 c c [m].7 affected flag(s) c rlca [m] rotate data memory left through carry with result in acc description data in the specified data memory and the carry flag are rotated left by 1 bit. bit 7 re - places the carry bit and the original carry flag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 c c [m].7 affected flag(s) c rr [m] rotate data memory right description the contents of the specified data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 affected flag(s) none rra [m] rotate data memory right with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 [m].0 affected flag(s) none rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry flag is rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 c c [m].0 affected flag(s) c rrca [m] rotate data memory right through carry with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit. bit 0 re - places the carry bit and the original carry flag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 c c [m].0 affected flag(s) c HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 109 march 3, 2011
sbc a,[m] subtract data memory from acc with carry description the contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] c affected flag(s) ov, z, ac, c sbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] c affected flag(s) ov, z, ac, c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are first decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruc - tion while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] 1 skip if [m] = 0 affected flag(s) none sdza [m] skip if decrement data memory is zero with result in acc description the contents of the specified data memory are first decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the spec- ified data memory contents remain unchanged. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc [m] 1 skip if acc = 0 affected flag(s) none set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ffh affected flag(s) none set [m].i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i 1 affected flag(s) none rev. 1.00 110 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa
siz [m] skip if increment data memory is 0 description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruc - tion while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m]+1 skip if [m] = 0 affected flag(s) none siza [m] skip if increment data memory is zero with result in acc description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the spec - ified data memory contents remain unchanged. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m]+1 skip if acc = 0 affected flag(s) none snz [m].i skip if bit i of data memory is not 0 description if bit i of the specified data memory is not 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruc- tion. operation skip if [m].i 0 affected flag(s) none sub a,[m] subtract data memory from acc description the specified data memory is subtracted from the contents of the accumulator. the re- sult is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] affected flag(s) ov, z, ac, c subm a,[m] subtract data memory from acc with result in data memory description the specified data memory is subtracted from the contents of the accumulator. the re - sult is stored in the data memory. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] affected flag(s) ov, z, ac, c sub a,x subtract immediate data from acc description the immediate data specified by the code is subtracted from the contents of the accumu - lator. the result is stored in the accumulator. note that if the result of subtraction is neg - ative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc x affected flag(s) ov, z, ac, c HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 111 march 3, 2011
swap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specified data memory are interchanged. operation [m].3~[m].0 [m].7 ~ [m].4 affected flag(s) none swapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specified data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain un - changed. operation acc.3 ~ acc.0 [m].7 ~ [m].4 acc.7 ~ acc.4 [m].3 ~ [m].0 affected flag(s) none sz [m] skip if data memory is 0 description if the contents of the specified data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation skip if [m] = 0 affected flag(s) none sza [m] skip if data memory is 0 with data movement to acc description the contents of the specified data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy in- struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] skip if [m] = 0 affected flag(s) none sz [m].i skip if bit i of data memory is 0 description if bit i of the specified data memory is 0, the following instruction is skipped. as this re - quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following in - struction. operation skip if [m].i = 0 affected flag(s) none tabrdc [m] read table (current page) to tblh and data memory description the low byte of the program code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none rev. 1.00 112 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa
tabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none xor a,[m] logical xor data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor [m] affected flag(s) z xorm a,[m] logical xor acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical xor operation. the result is stored in the data memory. operation [m] acc xor [m] affected flag(s) z xor a,x logical xor immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor x affected flag(s) z HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 113 march 3, 2011
package information 16-pin dip (300mil) outline dimensions ms-001d (see fig1) symbol dimensions in inch min. nom. max. a 0.780 0.880 b 0.240 0.280 c 0.115 0.195 d 0.115 0.150 e 0.014 0.022 f 0.045 0.070 g 0.100 h 0.300 0.325 i 0.430 symbol dimensions in mm min. nom. max. a 19.81 22.35 b 6.10 7.11 c 2.92 4.95 d 2.92 3.81 e 0.36 0.56 f 1.14 1.78 g 2.54 h 7.62 8.26 i 10.92 rev. 1.00 114 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa 7 7 / . / 8 $ ( ) * d b fig1. full lead packages 7 7 / . / 8 $ ( ) * d b fig2. 1 / 2 lead packages
ms-001d (see fig2) symbol dimensions in inch min. nom. max. a 0.735 0.775 b 0.240 0.280 c 0.115 0.195 d 0.115 0.150 e 0.014 0.022 f 0.045 0.070 g 0.100 h 0.300 0.325 i 0.430 symbol dimensions in mm min. nom. max. a 18.67 19.69 b 6.10 7.11 c 2.92 4.95 d 2.92 3.81 e 0.36 0.56 f 1.14 1.78 g 2.54 h 7.62 8.26 i 10.92 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 115 march 3, 2011
mo-095a (see fig2) symbol dimensions in inch min. nom. max. a 0.745 0.785 b 0.275 0.295 c 0.120 0.150 d 0.110 0.150 e 0.014 0.022 f 0.045 0.060 g 0.100 h 0.300 0.325 i 0.430 symbol dimensions in mm min. nom. max. a 18.92 19.94 b 6.99 7.49 c 3.05 3.81 d 2.79 3.81 e 0.36 0.56 f 1.14 1.52 g 2.54 h 7.62 8.26 i 10.92 rev. 1.00 116 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa
16-pin nsop (150mil) outline dimensions ms-012 symbol dimensions in inch min. nom. max. a 0.228 0.244 b 0.150 0.157 c 0.012 0.020 c 0.386 0.402 d 0.069 e 0.050 f 0.004 0.010 g 0.016 0.050 h 0.007 0.010 0 8 symbol dimensions in mm min. nom. max. a 5.79 6.20 b 3.81 3.99 c 0.30 0.51 c 9.80 10.21 d 1.75 e 1.27 f 0.10 0.25 g 0.41 1.27 h 0.18 0.25 0 8 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 117 march 3, 2011 / . / 8 $ ( ) * d b k
20-pin dip (300mil) outline dimensions ms-001d (see fig1) symbol dimensions in inch min. nom. max. a 0.980 1.060 b 0.240 0.280 c 0.115 0.195 d 0.115 0.150 e 0.014 0.022 f 0.045 0.070 g 0.100 h 0.300 0.325 i 0.430 symbol dimensions in mm min. nom. max. a 24.89 26.92 b 6.10 7.11 c 2.92 4.95 d 2.92 3.81 e 0.36 0.56 f 1.14 1.78 g 2.54 h 7.62 8.26 i 10.92 rev. 1.00 118 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa - 4 / / / / 4 $ ( ) * d b fig1. full lead packages - 4 / / / / 4 $ ( ) * d b fig2. 1 / 2 lead packages
mo-095a (see fig2) symbol dimensions in inch min. nom. max. a 0.945 0.985 b 0.275 0.295 c 0.120 0.150 d 0.110 0.150 e 0.014 0.022 f 0.045 0.060 g 0.100 h 0.300 0.325 i 0.430 symbol dimensions in mm min. nom. max. a 24.00 25.02 b 6.99 7.49 c 3.05 3.81 d 2.79 3.81 e 0.36 0.56 f 1.14 1.52 g 2.54 h 7.62 8.26 i 10.92 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 119 march 3, 2011
20-pin sop (300mil) outline dimensions ms-013 symbol dimensions in inch min. nom. max. a 0.393 0.419 b 0.256 0.300 c 0.012 0.020 c 0.496 0.512 d 0.104 e 0.050 f 0.004 0.012 g 0.016 0.050 h 0.008 0.013 0 8 symbol dimensions in mm min. nom. max. a 9.98 10.64 b 6.50 7.62 c 0.30 0.51 c 12.60 13.00 d 2.64 e 1.27 f 0.10 0.30 g 0.41 1.27 h 0.20 0.33 0 8 rev. 1.00 120 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa - 4 / / / / 4 $ ( ) * k d b
20-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.228 0.244 b 0.150 0.158 c 0.008 0.012 c 0.335 0.347 d 0.049 0.065 e 0.025 f 0.004 0.010 g 0.015 0.050 h 0.007 0.010 0 8 symbol dimensions in mm min. nom. max. a 5.79 6.20 b 3.81 4.01 c 0.20 0.30 c 8.51 8.81 d 1.24 1.65 e 0.64 f 0.10 0.25 g 0.38 1.27 h 0.18 0.25 0 8 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 121 march 3, 2011 - 4 / / / / 4 $ ( ) * k d b
24-pin skdip (300mil) outline dimensions ms-001d (see fig1) symbol dimensions in inch min. nom. max. a 1.230 1.280 b 0.240 0.280 c 0.115 0.195 d 0.115 0.150 e 0.014 0.022 f 0.045 0.070 g 0.100 h 0.300 0.325 i 0.430 symbol dimensions in mm min. nom. max. a 31.24 32.51 b 6.10 7.11 c 2.92 4.95 d 2.92 3.81 e 0.36 0.56 f 1.14 1.78 g 2.54 h 7.62 8.26 i 10.92 rev. 1.00 122 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa - 5 / / 6 / - $ ( ) * d b fig1. full lead packages - 5 / / 6 / - $ ( ) * d b fig2. 1 / 2 lead packages
ms-001d (see fig2) symbol dimensions in inch min. nom. max. a 1.160 1.195 b 0.240 0.280 c 0.115 0.195 d 0.115 0.150 e 0.014 0.022 f 0.045 0.070 g 0.100 h 0.300 0.325 i 0.430 symbol dimensions in mm min. nom. max. a 29.46 30.35 b 6.10 7.11 c 2.92 4.95 d 2.92 3.81 e 0.36 0.56 f 1.14 1.78 g 2.54 h 7.62 8.26 i 10.92 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 123 march 3, 2011
mo-095a (see fig2) symbol dimensions in inch min. nom. max. a 1.145 1.185 b 0.275 0.295 c 0.120 0.150 d 0.110 0.150 e 0.014 0.022 f 0.045 0.060 g 0.100 h 0.300 0.325 i 0.430 symbol dimensions in mm min. nom. max. a 29.08 30.10 b 6.99 7.49 c 3.05 3.81 d 2.79 3.81 e 0.36 0.56 f 1.14 1.52 g 2.54 h 7.62 8.26 i 10.92 rev. 1.00 124 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa
24-pin sop (300mil) outline dimensions ms-013 symbol dimensions in inch min. nom. max. a 0.393 0.419 b 0.256 0.300 c 0.012 0.020 c 0.598 0.613 d 0.104 e 0.050 f 0.004 0.012 g 0.016 0.050 h 0.008 0.013 0 8 symbol dimensions in mm min. nom. max. a 9.98 10.64 b 6.50 7.62 c 0.30 0.51 c 15.19 15.57 d 2.64 e 1.27 f 0.10 0.30 g 0.41 1.27 h 0.20 0.33 0 8 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 125 march 3, 2011 - 5 / / 6 / - $ ( ) * k d b
24-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.228 0.244 b 0.150 0.157 c 0.008 0.012 c 0.335 0.346 d 0.054 0.060 e 0.025 f 0.004 0.010 g 0.022 0.028 h 0.007 0.010 0 8 symbol dimensions in mm min. nom. max. a 5.79 6.20 b 3.81 3.99 c 0.20 0.30 c 8.51 8.79 d 1.37 1.52 e 0.64 f 0.10 0.25 g 0.56 0.71 h 0.18 0.25 0 8 rev. 1.00 126 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa - 5 / / 6 / - $ ( ) * k d b
28-pin skdip (300mil) outline dimensions symbol dimensions in inch min. nom. max. a 1.375 1.395 b 0.278 0.298 c 0.125 0.135 d 0.125 0.145 e 0.016 0.020 f 0.050 0.070 g 0.100 h 0.295 0.315 i 0.375 symbol dimensions in mm min. nom. max. a 34.93 35.43 b 7.06 7.57 c 3.18 3.43 d 3.18 3.68 e 0.41 0.51 f 1.27 1.78 g 2.54 h 7.49 8.00 i 9.53 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 127 march 3, 2011 7 7 - / / , / 5 $ ( ) * d b
28-pin sop (300mil) outline dimensions ms-013 symbol dimensions in inch min. nom. max. a 0.393 0.419 b 0.256 0.300 c 0.012 0.020 c 0.697 0.713 d 0.104 e 0.050 f 0.004 0.012 g 0.016 0.050 h 0.008 0.013 0 8 symbol dimensions in mm min. nom. max. a 9.98 10.64 b 6.50 7.62 c 0.30 0.51 c 17.70 18.11 d 2.64 e 1.27 f 0.10 0.30 g 0.41 1.27 h 0.20 0.33 0 8 rev. 1.00 128 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa - / / , / 5 $ ( ) * k d b
28-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.228 0.244 b 0.150 0.157 c 0.008 0.012 c 0.386 0.394 d 0.054 0.060 e 0.025 f 0.004 0.010 g 0.022 0.028 h 0.007 0.010 0 8 symbol dimensions in mm min. nom. max. a 5.79 6.20 b 3.81 3.99 c 0.20 0.30 c 9.80 10.01 d 1.37 1.52 e 0.64 f 0.10 0.25 g 0.56 0.71 h 0.18 0.25 0 8 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 129 march 3, 2011 - / / , / 5 $ ( ) * k d b
44-pin qfp (10mm 10mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.512 0.528 b 0.390 0.398 c 0.512 0.528 d 0.390 0.398 e 0.031 f 0.012 g 0.075 0.087 h 0.106 i 0.010 0.020 j 0.029 0.037 k 0.004 0.008 l 0.004 0 7 symbol dimensions in mm min. nom. max. a 13.00 13.40 b 9.90 10.10 c 13.00 13.40 d 9.90 10.10 e 0.80 f 0.30 g 1.90 2.20 h 2.70 i 0.25 0.50 j 0.73 0.93 k 0.10 0.20 l 0.10 0 7 rev. 1.00 130 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa 6 5 / / / 5 5 $ ( - - / - * d b l g 6 6 - 6 ) !
reel dimensions sop 16n (150mil) symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flange 16.8 +0.3/-0.2 t2 reel thickness 22.20.2 sop 20w, sop 24w, sop 28w (300mil) symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flange 24.8 +0.3/-0.2 t2 reel thickness 30.20.2 ssop 20s (150mil), ssop 24s (150mil), ssop 28s (150mil) symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flange 16.8 +0.3/-0.2 t2 reel thickness 22.20.2 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 131 march 3, 2011 $ (
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carrier tape dimensions sop 16n (150mil) symbol description dimensions in mm w carrier tape width 16.00.3 p cavity pitch 8.00.1 e perforation position 1.750.1 f cavity to perforation (width direction) 7.50.1 d perforation diameter 1.55 +0.10/-0.00 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 6.50.1 b0 cavity width 10.30.1 k0 cavity depth 2.10.1 t carrier tape thickness 0.300.05 c cover tape width 13.30.1 rev. 1.00 132 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa ' ) / ' / ' 4 ) * g 4 ( 4 $ 4 7 > 7 7 / 7 7 7 7 7 7 7 7 7 : 7 b
sop 20w symbol description dimensions in mm w carrier tape width 24.0 +0.3/-0.1 p cavity pitch 12.00.1 e perforation position 1.750.10 f cavity to perforation (width direction) 11.50.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 10.80.1 b0 cavity width 13.30.1 k0 cavity depth 3.20.1 t carrier tape thickness 0.300.05 c cover tape width 21.30.1 sop 24w symbol description dimensions in mm w carrier tape width 24.00.3 p cavity pitch 12.00.1 e perforation position 1.750.1 f cavity to perforation (width direction) 11.50.1 d perforation diameter 1.55 +0.10/-0.00 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 10.90.1 b0 cavity width 15.90.1 k0 cavity depth 3.10.1 t carrier tape thickness 0.350.05 c cover tape width 21.30.1 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 133 march 3, 2011
sop 28w (300mil) symbol description dimensions in mm w carrier tape width 24.00.3 p cavity pitch 12.00.1 e perforation position 1.750.10 f cavity to perforation (width direction) 11.50.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 10.850.10 b0 cavity width 18.340.10 k0 cavity depth 2.970.10 t carrier tape thickness 0.350.01 c cover tape width 21.30.1 ssop 20s (150mil) symbol description dimensions in mm w carrier tape width 16.0 +0.3/-0.1 p cavity pitch 8.00.1 e perforation position 1.750.10 f cavity to perforation (width direction) 7.50.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 6.50.1 b0 cavity width 9.00.1 k0 cavity depth 2.30.1 t carrier tape thickness 0.300.05 c cover tape width 13.30.1 rev. 1.00 134 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa
ssop 24s (150mil) symbol description dimensions in mm w carrier tape width 16.0 +0.3/-0.1 p cavity pitch 8.00.1 e perforation position 1.750.10 f cavity to perforation (width direction) 7.50.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 6.50.1 b0 cavity width 9.50.1 k0 cavity depth 2.10.1 t carrier tape thickness 0.300.05 c cover tape width 13.30.1 ssop 28s (150mil) symbol description dimensions in mm w carrier tape width 16.00.3 p cavity pitch 8.00.1 e perforation position 1.750.1 f cavity to perforation (width direction) 7.50.1 d perforation diameter 1.55 +0.10/-0.00 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 6.50.1 b0 cavity width 10.30.1 k0 cavity depth 2.10.1 t carrier tape thickness 0.300.05 c cover tape width 13.30.1 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa rev. 1.00 135 march 3, 2011
rev. 1.00 136 march 3, 2011 HT46R064G/065g/0662g enhanced a/d type 8-bit otp mcu with opa copyright 2011 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shenzhen sales office) 5f, unit a, productivity building, no.5 gaoxin m 2nd road, nanshan district, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor (usa), inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538, usa tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com

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